Device including a plurality of memory banks and a pipeline control circuit configured to execute a command on the plurality of memory banks
A method for carrying out read and write operations in a synchronous memory device having a shared I/O, includes receiving a read command directed to a first internal memory bank during a first timeslot, activating the first internal memory bank to access read data at a read address requested by the read command, receiving a write command directed to a second internal memory bank during a second timeslot later than the first timeslot, determining whether a data collision between the read data for output to the shared I/O with normal read latency and write data to be received on the shared I/O with normal write latency would occur, and receiving the write data on the shared I/O with the normal write latency during a third timeslot later than the second timeslot.
1. A method for carrying out read and write operations in a synchronous memory device having a shared I/O, the method comprising:
receiving a read command directed to a first internal memory bank during a first timeslot;
activating the first internal memory bank to access read data at a read address requested by the read command;
receiving a write command directed to a second internal memory bank during a second timeslot later than the first timeslot;
determining whether a data collision between the read data for output to the shared I/O with normal read latency and write data to be received on the shared I/O with normal write latency would occur;
receiving the write data on the shared I/O with the normal write latency during a third timeslot later than the second timeslot;
outputting, if it was determined that the data collision would not occur, the read data with the normal read latency on the shared I/O during a fourth timeslot;
activating the second internal memory bank to write the write data to a write address requested by the write command; and
outputting, if it was determined that the data collision would occur, the read data with read latency greater than the normal read latency to the shared I/O during a fifth timeslot later than the third timeslot.
2. The method as claimed in claim 1 , wherein the fourth timeslot is later than the third timeslot.
3. The method as claimed in claim 1 , wherein the fourth timeslot is earlier than the third timeslot.
4. The method as claimed in claim 1 , wherein each of the first to fifth timeslots have a duration of one clock period.
5. The method as claimed in claim 1 , wherein the normal read latency is equal to the sum of the normal write latency plus a bank waiting time.
6. The method as claimed in claim 1 , wherein the read and write commands are pipelined.
7. The method as claimed in claim 6 , wherein the first and second internal memory banks are sequentially accessed.
8. The method as claimed in claim 7 , wherein the read latency greater than the normal read latency is equal to the normal read latency plus a bank waiting time.
9. The method as claimed in claim 1 , wherein the read and write data are transferred between the first and second internal memory banks and the shared I/O over a shared read/write bus.
10. The method as claimed in claim 9 , wherein the read and write data are transferred over the shared read/write bus during a common timeslot, the read data being transferred over the shared read/write bus during one half of the common timeslot and the write data being transferred over the shared read/write bus during the other one half of the common timeslot.
11. The method as claimed in claim 1 , wherein the synchronous memory device is a DRAM.
12. The method as claimed in claim 11 , wherein the synchronous memory device is a 2T DRAM.
13. The method as claimed in claim 1 , wherein the synchronous memory device is a stacked memory device.
14. The method as claimed in claim 1 , wherein each of the first to fifth timeslots have a duration of not more than one clock period.