IP Library Granted Patent US 9,141,486
Granted Patent B2
US 9,141,486 · App. 14/179,667 · Granted Sep 22, 2015

Intelligent I/O cache rebuild in a storage controller

Inventors: Ramkumar Venkatachalam (Bangalore, IN); Sumanesh Sethuramachar Samanta (Bangalore, IN); Srikanth Sethuramachar Krishnamurthy (Bangalore, IN)
Assignee: Avago Technologies General IP (Singapore) Pte Ltd
G06F11/1666G06F11/20G06F12/0802G06F12/0866
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Quick Facts
Patent No.
US 9,141,486
App. No.
14/179,667
Granted
Sep 22, 2015
Kind
B2
Abstract

Systems and methods presented herein provide for redundancy in I/O caching. In one embodiment, a storage controller includes a first cache operable to receive input/output requests between a host system and a storage device, to compress data of the input/output requests, and to cache the compressed data before writing to the storage device. The storage controller also includes a second cache operable to track chunks of the compressed data in the first cache. When the first cache fails, the second cache is operable to cache the tracked chunks of the compressed data that have not been written to the storage device in a third cache while leaving chunks of data in the second cache that have been written to the storage device.

Claims (64)

1. A storage controller, comprising:

a first cache operable to receive input/output requests between a host system and a storage device, to compress data of the input/output requests, and to cache the compressed data before writing to the storage device; and

a second cache operable to:

track chunks of the compressed data in the first cache; and,

when the first cache fails, cache the tracked chunks of the compressed data that have not been written to the storage device in a third cache while leaving chunks of data in the second cache that have been written to the storage device.

2. The storage controller of claim 1 , further comprising:

a volatile memory operable to, when the first cache fails, store metadata associated with the chunks of the compressed data that have not been written to the storage device, the metadata being generated in response to tracking the chunks of the compressed data that have not been written to the storage device; and

a processor operable to detect when the first cache fails, to retrieve the chunks of the compressed data that have not been written to the storage device from the second cache, and to direct caching of the chunks of the compressed data that have not been written to the storage device in the third cache.

3. The storage controller of claim 2 , wherein:

the first cache and the second cache employ a Redundant Array of Independent Disks storage management of the compressed data.

4. The storage controller of claim 3 , further comprising:

a fourth cache; and

wherein:

the first, second and third caches implement striping in accordance with the Redundant Array of Independent Disks; and

the processor is further operable to rebuild valid chunks of data of the first cache in the fourth cache based on parity chunks located in the second and third caches.

5. The storage controller of claim 1 , wherein:

the first and the second caches are virtual caches configured from a same solid-state drive.

6. The storage controller of claim 1 , wherein:

the first cache is configured from a first solid-state drive; and

the second cache is configured from a second solid-state drive.

7. A method operable in a storage controller, comprising:

with a first cache:

receiving input/output requests between a host system and a storage device;

compressing data of the input/output requests; and

caching the compressed data before writing to the storage device; and

with a second cache:

tracking chunks of the compressed data in the first cache; and

when the first cache fails, caching the tracked chunks of the compressed data that have not been written to the storage device in a third cache while leaving chunks of data in the second cache that have been written to the storage device.

8. The method of claim 7 , further comprising:

when the first cache fails, storing metadata associated with the chunks of the compressed data that have not been written to the storage device in a volatile memory, the metadata being generated in response to tracking the chunks of the compressed data that have not been written to the storage device;

retrieving the chunks of the compressed data that have not been written to the storage device from the second cache; and

directing caching of the chunks of the compressed data that have not been written to the storage device in the third cache.

9. The method of claim 8 , further comprising:

implementing a Redundant Array of Independent Disks storage management of the compressed data with the first and second caches.

10. The method of claim 9 , further comprising:

implementing striping in accordance with the Redundant Array of Independent Disks in the first, second and third caches; and

rebuilding valid chunks of data of the first cache in a fourth cache based on parity chunks located in the second and third caches.

11. The method of claim 7 , further comprising:

configuring the first and second caches from a same solid-state drive.

12. The method of claim 7 , further comprising:

configuring the first cache from a first solid-state drive; and

configuring the second cache from a second solid-state drive.

13. A non-transitory computer readable medium comprising instructions that, when executed by a processor in a storage controller, direct the processor to:

with a first cache:

receive input/output requests between a host system and a storage device;

compress data of the input/output requests; and

cache the compressed data before writing to the storage device; and

with a second cache:

track chunks of the compressed data in the first cache; and

when the first cache fails, cache the tracked chunks of the compressed data that have not been written to the storage device in a third cache while leaving chunks of data in the second cache that have been written to the storage device.

14. The computer readable medium of claim 13 , further comprising instructions that direct the processor to:

when the first cache fails, store metadata associated with the chunks of the compressed data that have not been written to the storage device in a volatile memory, the metadata being generated in response to tracking the chunks of the compressed data that have not been written to the storage device;

retrieve the chunks of the compressed data that have not been written to the storage device from the second cache; and

direct caching of the chunks of the compressed data that have not been written to the storage device in the third cache.

15. The computer readable medium claim 14 , further comprising instructions that direct the processor to:

implement a Redundant Array of Independent Disks storage management of the compressed data with the first and second caches.

16. The computer readable medium of claim 15 , further comprising instructions that direct the processor to:

implement striping in accordance with the Redundant Array of Independent Disks in the first, second and third caches; and

rebuild valid chunks of data of the first cache in a fourth cache based on parity chunks located in the second and third caches.

17. The computer readable medium of claim 13 , further comprising instructions that direct the processor to:

configure the first and second caches from a same solid-state drive.

18. The computer readable medium of claim 13 , further comprising instructions that direct the processor to:

configure the first cache from a first solid-state drive; and

configure the second cache from a second solid-state drive.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR SUMANESH, SUMANESH PREVIOUSLY RECORDED ON REEL 032211 FRAME 0201. ASSIGNOR(S) HEREBY CONFIRMS THE SUMANESH SAMANTA. Recorded Feb 26, 2014
From: VENKATACHALAM, RAMKUMAR; SAMANTA, SUMANESH; KRISHNAMURTHY, SRIKANTH SETHURAMACHAR
To: LSI CORPORATION
Reel/Frame 032360/0387 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2014
From: VENKATACHALAM, RAMKUMAR; SUMANESH, SUMANESH; KRISHNAMURTHY, SRIKANTH SETHURAMACHAR
To: LSI CORPORATION
Reel/Frame 032211/0201 →
Continuity (2)
Provisional Application 61927892 · Jan 15, 2014
Related Publication 20150199244A1 · Jul 16, 2015