Interleaved multipath digital power amplification
In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.
1. A system comprising:
an interleaved bit-stream generator adapted to receive a first digital input signal and output a switching signal, the interleaved-bit-stream generator comprising:
a fractional-delay array adapted to receive the first digital input signal and output a plurality of fractionally delayed digital output signals;
a bit-stream generation array adapted to receive the plurality of fractionally delayed digital output signals and output a plurality of corresponding bit-streams; and
a serializer block adapted to receive the plurality of corresponding bit-streams and interleave the bit-streams to generate the switching signal, wherein a frequency of the switching signal is higher than a frequency of the first digital input signal.
2. The system of claim 1 , wherein:
the fractional-delay array comprises M fractional-delay filters, where M is an integer greater than 1;
the bit-stream generator array comprises P bit-stream generators;
each fractional-delay filter receives the first digital input signal, introduces a corresponding fractional delay Φ j , and outputs a corresponding fractionally delayed digital output signal v j ;
j corresponds to the integers from 1 to M;
each bit-stream generator receives a fractionally delayed output signal u i , based on the output of at least one corresponding fractional-delay filter, and generates a corresponding bit-stream x i ; and
l corresponds to the integers from 1 to P.
3. The system of claim 2 , wherein:
M=P; and
v j =u i .
4. The system of claim 3 , wherein:
M=P=8;
the first digital input signal has a digital frequency f;
the first digital input signal has a sampling period having N samples;
Φ 1 =0;
Φ 2 =4/4*π*f/N;
Φ 3 =2/4*π*f/N+π;
Φ 4 =6/4*π*f/N+π;
Φ 5 =1/4*π*f/N−π/2;
Φ 6 =5/4*π*f/N−π/2;
Φ 7 =3/4*π*f/N+π/2; and
Φ 8 =7/4*πf*N+π/2.
5. The system of claim 3 , wherein:
M=P=8;
the first digital input signal has a digital frequency f;
the first digital input signal has a sampling period having N samples;
Φ 1 =0;
Φ 2 =4/4*π*f/N;
Φ 3 =2/4*π*f/N+π;
Φ 4 =6/4*π*f/N+π;
Φ 5 =1/4*π*f/N+π/2;
Φ 6 =5/4*π*f/N+π/2;
Φ 7 =3/4*π*f/N+3π/2; and
Φ 8 =7/4*πf*N+3π/2.
6. The system of claim 2 , wherein:
M=2*P;
the fractional-delay array further comprises P adders; and
adder i adds the outputs v 2i-1 and v 2i of fractional-delay filter 2 i− 1 and fractional-delay filter 2 i , respectively, to generate fractionally delayed output signal u i .
7. The system of claim 6 , wherein:
P=8; and
M=16.
8. The system of claim 6 , wherein:
Φ 2i-1 is different from Φ 2i .
9. The system of claim 6 , wherein:
Φ 2i-1 is selected so that v 2i-1 is a lower-side-band component signal; and
Φ 2i is selected so that v 2i is an upper-side-band component signal.
10. The system of claim 1 , wherein the system is powered by one or more batteries.
11. A method comprising:
receiving, by an interleaved bit-stream generator, a first digital input signal, wherein the interleaved bit-stream generator comprises:
a fractional-delay array;
a bit-stream generation array; and
a serializer block;
receiving, by the fractional-delay array, the first digital input signal;
outputting, by the fractional-delay array, a plurality of fractionally delayed digital output signals;
receiving, by the bit-stream generation array, the plurality of fractionally delayed digital output signals;
outputting, by the bit-stream generation array, a plurality of corresponding bit-streams;
receiving, by the serializer block, the plurality of corresponding bit-streams;
interleaving, by the serializer block, the plurality of bit-streams to generate a corresponding switching signal, wherein a frequency of the switching signal is higher than a frequency of the first digital input signal; and
outputting, by the interleaved bit-stream generator, the switching signal.
12. The method of claim 11 , wherein:
the fractional-delay array comprises M fractional-delay filters, where M is an integer greater than 1;
the bit-stream generator array comprises P bit-stream generators;
j corresponds to the integers from 1 to M;
i corresponds to the integers from 1 to P; and
the method comprises:
receiving, by each fractional-delay filter, the first digital input signal,
introducing, by each fractional-delay filter, a corresponding fractional delay Φ i ;
outputting, by each fractional-delay filter, a corresponding fractionally delayed digital output signal v j ;
receiving, by each bit-stream generator, a fractionally delayed output signal u i , based on the output of at least one corresponding fractional-delay filter; and
generating, by each bit-stream generator, a corresponding bit stream x i .
13. The method of claim 12 , wherein:
M=P; and
v j =u i .
14. The method of claim 13 , wherein:
M=P=8;
the first digital input signal has a digital frequency f;
the first digital input signal has a sampling period having N samples;
Φ 1 =0;
Φ 2 =4/4*π*f/N;
Φ 3 =2/4*π*f/N+π;
Φ 4 =6/4*π*f/N+π;
Φ 5 =1/4*π*f/N−π/2;
Φ 6 =5/4*π*f/N−π/2;
Φ 7 =3/4*π*f/N+π/2; and
Φ 8 =7/4*π*f/N+π/2.
15. The method of claim 13 , wherein:
M=P=8;
the first digital input signal has a digital frequency f;
the first digital input signal has a sampling period having N samples;
Φ 1 =0;
Φ 2 =4/4*π*f/N;
Φ 3 =2/4*π*f/N+π;
Φ 4 =6/4*π*f/N+π;
Φ 5 =1/4*π*f/N+π/2;
Φ 6 =5/4*π*f/N+π/2;
Φ 7 =3/4*π*f/N+3π/2; and
Φ 8 =7/4*π*f/N+3π/2.
16. The method of claim 12 , wherein:
M−2*P;
the fractional-delay array further comprises P adders; and
the method further comprises adding, by adder i, the outputs v 2i-1 and v 2i of fractional-delay filter 2 i −1 and fractional-delay filter 2 i , respectively, to generate fractionally delayed output signal u i .
17. The method of claim 16 , wherein:
P=8; and
M=16.
18. The method of claim 16 , wherein:
Φ 2i-1 is different from Φ 2i .
19. The method of claim 16 , further comprising:
selecting Φ 2i-1 so that v 2i-1 is a lower-side-band component signal; and
selecting Φ 2i so that v 2i is an upper-side-band component signal.
20. A method comprising:
receiving a first digital input signal;
outputting a plurality of fractionally delayed digital output signals;
outputting a plurality of corresponding bit-streams;
interleaving the plurality of bit-streams to generate a corresponding switching signal, wherein a frequency of the switching signal is higher than a frequency of the first digital input signal; and
outputting the switching signal.