Semiconductor device that performs refresh operation
A method for refreshing memory cells in a DRAM includes receiving a refresh command, receiving a refresh mode specifying signal in synchronization with the refresh command, refreshing a first quantity of memory cells when the refresh mode specifying signal has a first value, and refreshing a second quantity of memory cells, at least double the first quantity, when the refresh mode specifying signal has a second value.
1. A method for refreshing memory cells in a DRAM comprising:
receiving a refresh command;
receiving a refresh mode specifying signal in synchronization with the refresh command;
refreshing a first quantity of memory cells when the refresh mode specifying signal has a first value; and
refreshing a second quantity of memory cells, at least double the first quantity, when the refresh mode specifying signal has a second value.
2. The method as claimed in claim 1 wherein the refresh mode specifying signal is a binary signal.
3. The method as claimed in claim 2 wherein the refresh mode specifying signal is an address signal.
4. The method as claimed in claim 1 wherein the second quantity of memory cells are refreshed simultaneously when the refresh mode specifying signal has the second value.
5. The method as claimed in claim 1 wherein the first quantity of memory cells are refreshed simultaneously when the refresh mode specifying signal has the first value.
6. The method as claimed in claim 5 wherein the second quantity of memory cells are refreshed sequentially, at each time refreshing the first quantity of memory cells, when the refresh mode specifying signal has the second value.
7. The method as claimed in claim 1 wherein the first quantity of memory cells are refreshed in a first number of sequential operations when the refresh mode specifying signal has the first value and the second quantity of memory cells are refreshed in a second number of sequential operations greater than the first number of sequential operations when the refresh mode specifying signal has the second value.
8. The method as claimed in claim 1 wherein the second quantity is a fixed value.
9. The method as claimed in claim 1 wherein the first quantity is programmable in a mode register.
10. The method as claimed in claim 9 wherein the first quantity is programmable as three different values.
11. The method as claimed in claim 10 wherein the three different values are encoded as two bits.
12. The method as claimed in claim 10 wherein the first quantity is programmable as either ½, ¼, or ⅛ the second quantity.