Process control monitor and technique for thick photo-resist photolithographic processes
A process control monitor for determination of alignment between layers of a semiconductor structure includes a patterned layer having a plurality of lines formed on a base layer, the plurality of lines enclosed within a circle. A photo-resist layer is deposited on top of the base layer and over the patterned layer. The photo-resist layer may be patterned to include an opening that exposes a portion of the base layer adjacent the patterned layer and that exposes a portion of the patterned layer. Alignment between the patterned layer and the patterned photo-resist layer may be determined according to a contrast between the exposed portion of the base layer and the exposed portion of the patterned layer.
1. A method of determining alignment between layers of a semiconductor structure, the method comprising:
forming a patterned layer having a plurality of lines on a first layer, wherein the plurality of lines are enclosed within a circle;
depositing a photo-resist layer on the first layer and over the patterned layer;
patterning the photo-resist layer to include an opening that exposes a portion of the first layer adjacent the patterned layer and that exposes a portion of the patterned layer; and
determining alignment between the patterned layer and the patterned photo-resist layer according to a contrast between the exposed portion of the first layer and the exposed portion of the patterned layer.
2. The method of claim 1 , wherein the plurality of lines comprises concentric circles.
3. The method of claim 1 , wherein the plurality of lines comprises intersecting lines perpendicular to each other.
4. The method of claim 1 , wherein the patterned photo-resist layer comprises a columnar portion of the photo-resist layer disposed within the opening and covering a central portion of the patterned layer.
5. The method of claim 1 , wherein the exposed portion of the first layer surrounds a periphery of the patterned layer.
6. The method of claim 1 , wherein the patterned layer surrounds a periphery of the exposed portion of the first layer.
7. The method of claim 6 , wherein the patterned photo-resist layer comprises a columnar portion of the photo-resist layer disposed within the opening and covering a central portion of the exposed portion of the first layer.
8. The method of claim 1 , wherein the photo-resist layer has a thickness of at least 50 microns.
9. The method of claim 1 , wherein the photo-resist comprises dry film photo-resist.
10. The method of claim 1 , wherein the patterned layer comprises a metal.
11. The method of claim 1 , wherein the opening is square-shaped.
12. The method of claim 1 , wherein the opening is cylindrical-shaped.
13. The method of claim 1 , wherein the first layer comprises a semiconductor layer.
14. A process control monitor for a semiconductor device comprising:
a patterned layer having a plurality of lines on a first layer, wherein the plurality of lines are enclosed within a circle; and
a patterned photo-resist layer on the first layer and over the patterned layer,
the patterned photo-resist layer including an opening exposing a portion of the first layer adjacent the patterned layer and exposing a portion of the patterned layer.
15. The process control monitor of claim 14 , wherein the plurality of lines comprises concentric circles.
16. The process control monitor of claim 14 , wherein the plurality of lines comprises intersecting lines perpendicular to each other.
17. The process control monitor of claim 14 , wherein the patterned photo-resist layer comprises a columnar portion within the opening and covering a central portion of the patterned layer.
18. The process control monitor of claim 14 , wherein the exposed portion of the first layer surrounds a periphery of the patterned layer.
19. The process control monitor of claim 14 , wherein the patterned layer surrounds a periphery of the exposed portion of the first layer.
20. The process control monitor of claim 14 , wherein the patterned photo-resist layer comprises a columnar portion disposed within the opening and covering a central portion of the exposed portion of the first layer.
21. The process control monitor of claim 14 , wherein the patterned layer comprises a metal.
22. The process control monitor of claim 14 , wherein the opening is square-shaped.
23. The process control monitor of claim 14 , wherein the opening is cylindrical-shaped.
24. The process control monitor of claim 14 , wherein the first layer comprises a semiconductor layer.