Method and apparatus for feed forward equalizer with variable cursor position
A reconfigurable P-way parallel N-tap feed forward equalizer includes an adaptive filter configured to generate a series of coefficients (taps) and an input register for storing input symbols. A variable cursor position defined by a parameter corresponding to a position in the input register selects a set of pre-cursor and post-cursor taps for dynamic ISI correction of a like set of pre-cursor and post-cursor symbols. Multiplier banks generate partial result symbols by applying the taps to the set of input symbols, and a set of combiners or adder banks generate equalized output symbols from the partial result symbols. Two multiplexers adjust input symbols and coefficients according to the parameter, and a controller allows selection of an optimal parameter, and thus an optimal variable cursor position. The coefficient corresponding to the parameter may additionally be preset to save storage space.
1. An apparatus for equalization of input signals including at least one input symbol in a communications channel, comprising:
an adaptive filter configured to generate a plurality of coefficients;
at least one feed forward equalizer configured to receive and store a plurality of input symbols for correction of inter-symbol interference and including:
(a) an input register including a plurality of register positions, each register position configured to store an input symbol of the plurality of input symbols;
(b) a variable cursor position defined by a parameter corresponding to a register position of the plurality of register positions, configured to select a first plurality of pre-cursor coefficients and a second plurality of post-cursor coefficients from the plurality of coefficients;
(c) a plurality of multiplier banks configured to generate a plurality of partial result symbols by applying the plurality of coefficients to the plurality of input symbols; and
(d) at least one adder bank configured to generate a plurality of equalized output symbols by combining elements of the plurality of partial result symbols corresponding to each input symbol of the plurality of input symbols;
a first multiplexer configured to adjust the plurality of input symbols according to the parameter;
a second multiplexer configured to adjust the plurality of coefficients according to the parameter; and
a controller configured to choose the value of the parameter from a set of possible values.
2. The apparatus of claim 1 , wherein the apparatus is embodied in a serializer-deserializer (SerDes) receiver device.
3. The apparatus of claim 1 , wherein the at least one feed forward equalizer has N coefficients and level of parallelism P, where N and P are positive integers.
4. The apparatus of claim 3 , wherein:
the plurality of input symbols consists of a set of P input symbols;
the plurality of multiplier banks consists of a set of P multiplier banks;
the plurality of partial result symbols consists of a set of P partial result symbols; and
the plurality of equalized output symbols consists of a set of P equalized output symbols.
5. The apparatus of claim 3 , wherein the plurality of possible values of the parameter consists of the continuous range of integers from zero to N−1.
6. The apparatus of claim 1 , wherein the adaptive filter is configured to set the coefficient corresponding to the parameter to a constant value.
7. A method for equalizing input signals in a communications channel, comprising:
receiving a plurality of input symbols;
storing the plurality of input symbols in a plurality of register positions in a feed forward equalizer, the feed forward equalizer having a variable cursor position defined by a parameter corresponding to a register position of the plurality of register positions;
selecting the value of the parameter from a plurality of possible values;
adjusting the plurality of input symbols according to the parameter;
adjusting a plurality of coefficients, including a plurality of pre-cursor coefficients and a plurality of post-cursor coefficients, according to the parameter;
applying the plurality of coefficients to the plurality of input symbols to generate a plurality of partial result symbols via the feed forward equalizer; and
combining elements of the plurality of partial result symbols corresponding to each input symbol of the plurality of input symbols to generate a plurality of equalized output symbols via the feed forward equalizer.
8. The method of claim 7 , wherein the feed forward equalizer is embodied in a serializer-deserializer (SerDes) receiver device.
9. The method of claim 7 , wherein adjusting the plurality of input symbols according to the parameter includes adjusting the set of input symbols according to the parameter via a first multiplexer.
10. The method of claim 7 , wherein adjusting the plurality of coefficients according to the parameter includes adjusting the plurality of coefficients according to the parameter via a second multiplexer.
11. The method of claim 7 , wherein the feed forward equalizer has N coefficients and level of parallelism P, where N and P are positive integers.
12. The method of claim 11 , wherein:
the plurality of input symbols consists of a set of P input symbols;
the plurality of partial result symbols consists of a set of P partial result symbols; and
the plurality of equalized output symbols consists of a set of P equalized output symbols.
13. The method of claim 11 , wherein the plurality of possible values of the parameter consists of the continuous range of integers from zero to N−1.
14. The method of claim 7 , wherein the coefficient corresponding to the parameter is preset to a constant value.
15. A computer program product consisting of a non-transitory, computer-readable medium bearing code executable by a computing device or processor encoded thereon, the code including instructions for implementing a method, the method comprising:
receiving a plurality of input symbols;
storing the plurality of input symbols in a plurality of register positions in a feed forward equalizer, the feed forward equalizer having a variable cursor position defined by a parameter corresponding to a register position of the plurality of register positions;
selecting the value of the parameter from a plurality of possible values;
adjusting the plurality of input symbols according to the parameter;
adjusting a plurality of coefficients, including a plurality of pre-cursor coefficients and a plurality of post-cursor coefficients, according to the parameter;
applying the plurality of coefficients to the plurality of input symbols to generate a plurality of partial result symbols via the feed forward equalizer; and
combining elements of the plurality of partial result symbols corresponding to each input symbol of the plurality of input symbols to generate a plurality of equalized output symbols via the feed forward equalizer.