Semiconductor device including a clock generating circuit for generating an internal signal having a coarse delay line, a fine delay line and a selector circuit
View Patent ↗A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the ODT operation in which strict phase control is not required can be reduced.
1. A method for controlling a delay locked loop in a synchronous memory device, the delay locked loop having a delay line, and the method comprising:
receiving an external clock signal;
applying the external clock signal to the input of the delay line;
in response to a read command:
configuring the delay locked loop in a first mode of operation to provide an internal clock, from an output of the delay line to an output circuit, locked to the external clock; and
configuring the output circuit to output read data to an output terminal in synchronization with the internal clock; and
in response to an on-die-termination command:
configuring the delay locked loop in a second mode of operation to provide the internal clock locked to the external clock to the output circuit; and
configuring the output circuit to terminate the output terminal in synchronization with the internal clock; and
the delay locked loop controls the phase of the internal clock in a more precise manner in the first mode of operation compared to the second mode of operation, and
the delay locked loop consumes less power in the second mode of operation as compared to the first mode of operation.
2. The method as claimed in claim 1 wherein operation of a portion of the delay locked loop is enabled in the first mode of operation and operation of the portion of the delay locked loop is suspended in the second mode of operation.
3. The method as claimed in claim 2 wherein the portion of the delay locked loop is a fine delay line forming a portion of the delay line.
4. The method as claimed in claim 1 further comprising:
dividing the external clock to provide a sampling clock to update a counter which selects one of a plurality of outputs of the delay line, and
wherein the external clock is divided by a greater amount in the second mode of operation than in the first mode of operation.
5. The method as claimed in claim 1 further comprising:
dividing the output of the delay line to provide a replica clock for comparison with the external clock in a phase comparing circuit of the delay locked loop, and
wherein the output of the delay line is divided by a greater amount in the second mode of operation than in the first mode of operation.
6. The method as claimed in claim 5 wherein the output of the delay line is divided by one in the first mode of operation.
7. The method as claimed in claim 1 , wherein the delay locked loop includes a first portion and a second portion, wherein the first and second portions are enabled in the first mode of operation and operation of the second portion is suspended in the second mode of operation.
8. The method as claimed in claim 7 , wherein the second portion of the delay locked loop is a fine delay line and the first portion of the delay locked loop is a coarse delay line, the coarse delay line having a pitch adjustment that is greater than the fine delay line.