Driver IC for a display panel with touch device with display state timing in accordance with differing driving periods

1. A driver IC that performs a display by driving a plurality of signal electrodes for each display line of a display panel comprising:

a driving circuit that drives the signal electrodes; and

a driving control circuit that controls the driving circuit by dividing one display frame period into a plurality of display driving periods, in which non-display driving periods each follow the display driving period, and dummy driving periods each of which follows the non-display driving period and is prefixed to a next display driving period, wherein the plurality of display driving periods, at least one non-display driving period, and at least one dummy driving period is included between a back porch and a front porch in one display frame period, wherein each said display driving period is one period during which the driving control circuit serially selects a plurality of display lines,

wherein the driving control circuit selects the display line and causes the driving circuit to drive the plurality of signal electrodes using corresponding display data for each display line selected, during the display driving period,

wherein the driving control circuit does not select the display line and causes the driving circuit to stop a driving of the signal electrodes, during the non-display driving period,

wherein the driving control circuit causes the driving circuit to start the driving of the signal electrodes using dummy data changed from the display data at a time of a driving stop of the non-display driving period, during the dummy driving period,

wherein the driving control circuit includes, a display RAM that stores the display data, an address generation circuit that generates a read address of the display RAM, and an address control circuit that controls generation of the read address performed by the address generation circuit,

wherein the address control circuit includes, a line counter that counts up a line count clock by a display frame unit for each display line cycle designated; a dummy line counter that counts down a dummy line count clock from an initial value for each dummy line cycle designated; and a state control circuit that controls states of the display driving period, the non-display driving period, and the dummy driving period according to a count value of the line counter,

wherein the address generation circuit includes a display read address counter that counts up the line count clock,

wherein the state control circuit, causes the read address to be generated by counting up the display read address counter during the display driving period, stops a count operation of the display read address counter in a case that transition from the display driving period to the non-display driving period is performed, causes a count operation of the dummy line counter to be performed during a stop of the count operation of the display read address counter, and causes a read address of dummy data to be performed by subtracting the count value from a count value of the display read address counter which is stopped, and

wherein the address control circuit performs, a control that updates the read address during the display driving period in synchronization with a display line cycle which is a switching cycle of the display line, and a control that retroactively reads a read address updated during an end of the display driving period and another read address retroactively applied on a basis of the read address, and updates the read addresses as a read address in the dummy driving period.

2. The driver IC according to claim 1 ,

wherein the address generation circuit further includes, a subtraction circuit that subtracts a down count value obtained by counting down the dummy line count clock from the initial value during the stop of the count operation of the display read address counter, from the count value of the display read address counter which is updated during the end of the display driving period, and an address selector that selects the count value of the display read address counter during the display driving period, and selects an output of the subtraction circuit during the dummy driving period and sets a read output as the read address.

3. The driver IC according to claim 2 , further comprising:

a display line cycle counter that generates the line count clock for each cycle according to a preset value;

a dummy line cycle counter that generates the dummy line count clock for each cycle according to the preset value;

a first cycle selector that selects a first preset value which designates the display line cycle for the display driving period, or a second preset value which designates the display line cycle for the non-display driving period and the dummy driving period, as the preset value of the display line cycle counter; and

a second cycle selector that selects a third preset value which designates a dummy display line cycle for the dummy driving period, or a fourth preset value which designates the dummy display line cycle for the non-display driving period as the preset value of the dummy display line cycle counter.

4. The driver IC according to claim 3 , wherein

the state control circuit performs a selection control of the first cycle selector and the second cycle selector.

5. The driver IC according to claim 4 , wherein

the display line cycle for the non-display driving period and the dummy driving period is equal to a sum of the dummy display line cycle for the non-display driving period and a cycle of an integer multiple of the dummy display line cycle for the dummy driving period, and

the first preset value and the third preset value are a same value.

6. The driver IC according to claim 5 , further comprising:

a register circuit that rewritably sets control data for determining the first preset value to the fourth preset value.

7. The driver IC according to claim 1 , further comprising:

a register circuit that rewritably sets control data for designating the display driving period, the non-display driving period, and the dummy driving period using the count value of the line counter.

8. A driver IC comprising:

a display driver that performs a display by driving a plurality of signal electrodes for each display line of a display panel; and

a touch panel controller which can perform a touch detection by driving the touch panel during a non-display driving period performed by the display driver, wherein

the display driver includes

a driving circuit that drives the signal electrodes; and

a driving control circuit that controls the driving circuit by dividing one display frame period into a plurality of display driving periods, at least one non-display period, and at least one dummy driving period, each said non-display driving period following the display driving period, and each said dummy driving period following the non-display driving period and being prefixed to a next display driving period, the plurality of display driving periods, at least one non-display driving period, and at least one dummy driving period being included between a back porch and a front porch in one display frame period, wherein each said display driving period is one period during which the driving control circuit serially selects a plurality of display lines,

the driving control circuit selects the display line and causes the driving circuit to drive the plurality of signal electrodes using corresponding display data for each display line selected, during the display driving period,

the driving control circuit does not select the display line and causes the driving circuit to stop a driving of the signal electrodes, during the non-display driving period,

the driving control circuit causes the driving circuit to start the driving of the signal electrodes using dummy data changed from the display data at a time of a driving stop of the non-display driving period, during the dummy driving period,

the driving control circuit includes, a display RAM that stores the display data, an address generation circuit that generates a read address of the display RAM, and an address control circuit that controls generation of the read address performed by the address generation circuit,

the address control circuit includes, a line counter that counts up a line count clock by a display frame unit for each display line cycle designated; a dummy line counter that counts down a dummy line count clock from an initial value for each dummy line cycle designated; and a state control circuit that controls states of the display driving period, the non-display driving period, and the dummy driving period according to a count value of the line counter,

the address generation circuit includes a display read address counter that counts up the line count clock, and

the state control circuit, causes the read address to be generated by counting up the display read address counter to count up during the display driving period, stops a count operation of the display read address counter in a case that transition from the display driving period to the non-display driving period is performed, causes a count operation of the dummy line counter to be performed during a stop of the count operation of the display read address counter, and causes a read address of dummy data to be performed by subtracting the count value from a count value of the display read address counter which is stooped.

9. The driver IC according to claim 8 , wherein

the state control circuit determines the display driving period, the non-display driving period, and the dummy driving period by comparing the count value of the line counter with reference data.

10. The driver IC according to claim 9 , further comprising:

a register circuit that rewritably sets the reference data for determining the display driving period, the non-display driving period, and the dummy driving period.

11. The driver IC according to claim 8 , wherein

the address generation circuit further includes, a subtraction circuit that subtracts a down count value obtained by counting down the dummy line count clock from the initial value during the stop of the count operation of the display read address counter, from the count value of the display read address counter which is updated during the end of the display driving period; and an address selector that selects the count value of the display read address counter during the display driving period, and selects an output of the subtraction circuit during the dummy driving period and sets a read output as the read address.

12. The driver IC according to claim 11 , further comprising:

a display line cycle counter that generates the line count clock for each cycle according to a preset value;

a dummy line cycle counter that generates the dummy line count clock for each cycle according to the preset value;

a first cycle selector that selects a first preset value which designates the display line cycle for the display driving period, or a second preset value which designates the display line cycle for the non-display driving period and the dummy driving period, as the preset value of the display line cycle counter; and

a second cycle selector that selects a third preset value which designates a dummy display line cycle for the dummy driving period, or a fourth preset value which designates the dummy display line cycle for the non-display driving period as the preset value of the dummy display line cycle counter, wherein

the state control circuit performs a selection control of the first cycle selector and the second cycle selector.

13. The driver IC according to claim 12 , wherein

the display line cycle for the non-display driving period and the dummy driving period is equal to a sum of the dummy display line cycle for the non-display driving period and a cycle of an integer multiple of the dummy display line cycle for the dummy driving period, and

the first preset value and the third preset value are set to a same value.