VTFT formation using selective area deposition
View Patent ↗A method of producing a vertical transistor includes providing a conductive gate structure having a reentrant profile on a substrate. A conformal insulating material layer is formed on the conductive gate structure. A conformal semiconductor material layer is formed on the insulating material layer. A deposition inhibiting material is deposited over a portion of the substrate and the conductive gate structure including filling the reentrant profile. A portion of the deposition inhibiting material is removed without removing all of the deposition inhibiting material from the reentrant profile. A plurality of electrodes is formed by depositing an electrically conductive material layer on portions of the semiconductor material layer using a selective area deposition process in which the electrically conductive material layer is not deposited on the deposition inhibiting material remaining in the reentrant profile.
1. A method of producing a vertical transistor comprising:
providing a conductive gate structure having a reentrant profile on a substrate;
forming a conformal insulating material layer on the conductive gate structure;
forming a conformal semiconductor material layer on the insulating material layer;
depositing a deposition inhibiting material over a portion of the substrate and the conductive gate structure including filling the reentrant profile;
removing a portion of the deposition inhibiting material without removing all of the deposition inhibiting material from the reentrant profile; and
forming a plurality of electrodes by depositing an electrically conductive material layer on portions of the semiconductor material layer using a selective area deposition process in which the electrically conductive material layer is not deposited on the deposition inhibiting material remaining in the reentrant profile.
2. The method of claim 1 , wherein the selective area deposition process is a conformal deposition process.
3. The method of claim 2 , wherein the conformal deposition process is an atomic layer deposition process.
4. The method of claim 2 , wherein the conformal deposition process is a spatial atomic layer deposition process.
5. The method of claim 1 , wherein the reentrant profile protects the deposition inhibiting material during a deposition inhibiting material removal process that includes exposing and developing a photo-sensitive deposition inhibiting material.
6. The method of claim 1 , wherein the reentrant profile protects the deposition inhibiting material during a deposition inhibiting material removal process that includes directionally etching the deposition inhibiting material.
7. The method of claim 6 , wherein the directionally etching the deposition inhibiting material includes using an anisotropic plasma etching process.
8. The method of claim 1 , wherein depositing the deposition inhibiting material over the portion of the substrate and the conductive gate structure includes using a coating process.
9. The method of claim 1 , further comprising removing the deposition inhibiting material after depositing the electrically conducting material layer over portions of the semiconductor material layer.
10. The method of claim 1 , wherein the deposition inhibiting material is a polymer.
11. The method of claim 9 , wherein the polymer is polymethyl methacrylate (PMMA).