Forming a VTFT gate using printing
A method of forming a gate layer of a thin film transistor includes providing a substrate including a gate structure having a reentrant profile. A conformal conductive inorganic thin film is deposited over the gate structure. A polymeric resist is printed that wicks along the reentrant profile of the gate structure. The conformal conductive inorganic thin film is etched in areas not protected by the polymeric resist to form a patterned conductive gate layer located in the reentrant profile of the gate structure.
1. A method of forming a gate layer of a thin film transistor comprising:
providing a substrate including a gate structure having a reentrant profile;
depositing a conformal conductive inorganic thin film over the gate structure;
printing a polymeric resist that wicks along the reentrant profile of the gate structure due to capillary action; and
etching the conformal conductive inorganic thin film in areas not protected by the polymeric resist to form a patterned conductive gate layer located in the reentrant profile of the gate structure.
2. The method of claim 1 , further comprising treating the polymeric resist after printing the polymeric resist.
3. The method of claim 2 , wherein treating the polymeric resist includes using an oxygen plasma process.
4. The method of claim 1 , wherein printing the polymeric resist includes printing with an inkjet printing process or a flexographic printing process.
5. The method of claim 1 , further comprising depositing another conformal dielectric layer on the gate structure before depositing the conformal conductive thin film.
6. The method of claim 1 , further comprising exposing the polymeric resist from a side of the polymeric resist opposite the substrate such that the polymeric resist in the reentrant profile remains unexposed.
7. The method of claim 1 , further comprising removing the polymeric resist after etching the conformal conductive inorganic thin film.
8. The method of claim 1 , wherein providing the substrate includes providing a patterned conductive layer on the substrate prior to providing the gate structure.