IP Library Granted Patent US 9,165,564
Granted Patent B2
US 9,165,564 · App. 14/198,738 · Granted Oct 20, 2015

Method and apparatus for frame-based buffer control in a communication system

Inventors: Christof Faller (Murray Hill, NJ); Raziel Haimi-Cohen (Springfield, NJ)
Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
G10L19/167H04H60/27H04J3/0632H04J3/1688H04H2201/20H04N19/152
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,165,564
App. No.
14/198,738
Granted
Oct 20, 2015
Kind
B2
Abstract

A digital audio broadcasting (DAB) communication system with a decoder buffer specified by a maximum number of encoded frames is disclosed. A predicted number of encoded frames, F pred , in the decoder is sent to a receiver with audio data. If the decoder buffer level becomes too high, additional bits are allocated to each frame for each of N programs. If the decoder buffer level becomes too low, fewer bits are allocated to each frame for each of the N programs. F pred can also be employed to (i) enable the decoder; and (ii) synchronize the transmitter and the receiver. The receiver fills the decoder buffer with F pred frames before commencing decoding frames. The transmitter and receiver clocks may be synchronized with a feedback loop that compares the actual level of the decoder buffer to the predicted value, F pred , received from the transmitter.

Claims (25)

1. A system for adjusting a rate controller in a communication system, comprising:

a memory that stores non-transitory computer-readable code; and

a processor operatively coupled to said memory, said processor configured to execute said non-transitory computer-readable code, said non-transitory computer-readable code configured to direct the processor to:

receive a predicted number of encoded frames in a buffer, wherein said predicted number of encoded frames considers a respective data rate of an encoder and a decoder and a channel bit rate of said communication system;

compare said predicted number of encoded frames to an actual number of encoded frames in said buffer to generate a result; and

apply a control signal from a rate controller in response to the result.

2. The system of claim 1 , wherein said processor is further configured to adjust a clock frequency based on said result.

3. The system of claim 2 , wherein said processor is further configured to increase said clock frequency if said predicted number of encoded frames is lower than said actual number of encoded frames in said buffer.

4. The system of claim 2 , wherein said processor is further configured to decrease said clock frequency if said predicted number of encoded frames is higher than said actual number of encoded frames in said buffer.

5. The system of claim 1 , wherein a controller is configured to determine when to commence a decoding of said frames using said predicted number of encoded frames.

6. The system of claim 5 , wherein a controller waits approximately said predicted number of encoded frames before decoding said frames after a decoder is first started.

7. The system of claim 5 , wherein a controller waits approximately said predicted number of encoded frames before decoding said frames after a new program is selected.

8. The system of claim 1 , wherein said communication system is a digital audio broadcasting system.

9. The system of claim 1 , wherein said predicted number of encoded frames is computed by the rate controller.

10. A system for adjusting an input to a buffer in a communication system, comprising:

a buffer for storing frames of encoded data; and

a rate controller that receives a predicted number of encoded frames in the buffer, wherein said predicted number of encoded frames considers a respective data rate of an encoder and a decoder and a channel bit rate of said communication system the rate controller arranged to compare said predicted number of encoded frames to an actual number of encoded frames in said buffer and adjust the bit rate upstream of the input to the buffer in response to a result.

11. The system of claim 10 , wherein the rate controller adjusts a clock frequency based on said result.

12. The system of claim 11 , wherein the clock frequency is increased when said predicted number of encoded frames is lower than said actual number of encoded frames in said buffer.

13. The system of claim 11 , wherein the clock frequency is decreased when said predicted number of encoded frames is higher than said actual number of encoded frames in said buffer.

14. The system of claim 10 , further comprising a controller configured to determine when to commence a decoding of said frames using said predicted number of encoded frames.

15. The system of claim 14 , wherein said controller waits approximately said predicted number of encoded frames before decoding said frames after a decoder is first started.

16. The system of claim 14 , wherein said controller waits approximately said predicted number of encoded frames before decoding said frames after a new program is selected.

17. The system of claim 10 , wherein said communication system is a digital audio broadcasting system.

18. The system of claim 10 , wherein said predicted number of encoded frames is computed by the rate controller.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
Continuity (3)
Continuation 12262239 · Oct 31, 2008
Division 09895926 · Jun 29, 2001
Related Publication 20140188489A1 · Jul 3, 2014