Systems and methods for multi-head separation determination
View Patent ↗Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.
1. A method for determining separation between read heads, the method comprising:
receiving a first data set corresponding to information received from a first read head and sampled at a sample rate;
identifying a sector address mark in the first data set using a first detection circuit;
receiving a second data set corresponding to information received from a second read head;
identifying the sector address mark in the second data set using a second detection circuit and sampled at the sample rate; and
calculating an integer number of periods of the sample rate within a difference between a location of the sector address mark in the first data set and a location of the sector address mark in the second data set.
2. The method of claim 1 , wherein the method further comprises:
determining a phase of the first data set;
determining a phase of the second data set; and
calculating a factional offset based at least in part on the phase of the first data set and the phase of the second data set.
3. The method of claim 2 , wherein the fractional offset corresponds to a distance that is a fraction of a distance covered by one period of the sample rate.
4. The method of claim 2 , wherein the method further comprises:
calculating the factional offset during a first operational mode and during a second operational mode; and
calculating the integer number of periods of the sample rate during the first operational mode and not during the second operational mode.
5. The method of claim 4 , wherein the first operational mode is a start up mode where an offset between the first read head and the second read head is likely to incur more than a fraction of the period of the sample rate, and wherein the second operational mode is a steady state mode where the offset is unlikely to change more than a fraction of the period of the sample rate between consecutive updates of the offset.
6. The method of claim 2 , wherein calculating the fractional offset comprises:
subtracting the phase of the first data set from the phase of the second data set to yield a phase difference.
7. The method of claim 6 , wherein the phase difference is the fractional offset.
8. The method of claim 6 , wherein calculating the fractional offset further comprises:
subtracting a prior instance of the phase difference from a current instance of the phase difference to yield a first error;
subtracting the fractional offset from the current instance of the phase difference to yield a second error;
adding an input derived from the first error to a slope estimate to yield a slope input;
integrating the slope input to update the slope estimate;
adding the slope estimate, the fractional offset and an input derived from the second error to yield a delay input; and
integrating the delay input to update the fractional offset.
9. The method of claim 8 , wherein calculating the fractional offset further comprises:
calculating a running average of the first error to yield an average error; and
multiplying the average error by a first gain value to yield the input derived from the first error; and multiplying the second error by a second gain value to yield the input derived from the second error.
10. The method of claim 9 , wherein the method further comprises:
selecting the first gain value based at least in part on the second error; and
selecting the first gain value based at least in part on the second error.
11. The method of claim 2 , wherein the sample rate corresponds to a clock used to process data from a servo data region, and wherein the method further comprises:
converting a combination of the integer number of periods of the sample rate and the fractional offset to a number of periods of a clock used to process data derived from a region other than the servo data region.
12. A data processing system, the data processing system comprising:
a first sector address mark detection circuit operable to detect the location of a sector address mark in a first data set derived from a first read head and sampled at a sample rate;
a second sector address mark detection circuit operable to detect the location of the sector address mark in a second data set derived from a first read head and sampled at a sample rate; and
an integer distance calculation circuit operable to calculate an integer number of periods of the sample rate within a difference between a location of the sector address mark in the first data set and a location of the sector address mark in the second data set.
13. The data processing system of claim 12 , the system further comprising:
a first phase detection circuit operable to determine a phase of the first data set;
a second phase detection circuit operable to determine a phase of the second data set; and
a fractional offset calculation circuit operable to calculate a fractional offset of the first read head from the second read head based at least in part on the phase of the first data set.
14. The system of claim 13 , wherein the fractional offset corresponds to a distance that is a fraction of a distance covered by one period of the sample rate.
15. The system of claim 13 , wherein the fractional offset calculation circuit includes a summation circuit operable to subtract the phase of the first data set from the phase of the second data set to yield a phase difference.
16. The system of claim 15 , wherein the phase difference is the fractional offset.
17. The system of claim 15 , wherein the summation circuit is a first summation circuit, and wherein the fractional offset calculation circuit further comprises:
a second summation circuit operable to subtract a prior instance of the phase difference from a current instance of the phase difference to yield a first error;
a third summation circuit operable to subtract the fractional offset from the current instance of the phase difference to yield a second error;
a fourth summation circuit operable to add an input derived from the first error to a slope estimate to yield a slope input;
a first integration circuit operable to integrate the slope input to update the slope estimate;
a fifth summation circuit operable to add an input derived from the second error to the slope estimate and the fractional offset to yield a delay input; and
a second integration circuit operable to integrate the delay input to update the fractional offset.
18. The system of claim 17 , wherein the system further comprises:
an averaging circuit operable to calculate a running average of the first error to yield an average error;
a first multiplying circuit operable to multiply the average error by a first gain value to yield the input derived from the first error; and
a second multiplying circuit operable to multiply the second error by a second gain value to yield the input derived from the second error.
19. The system of claim 18 , wherein the system further comprises:
a gain selection circuit operable to select the first gain value and the second gain value based at least in part on the second error.
20. The system of claim 12 , wherein the system is implemented as part of a storage device.
21. The system of claim 20 , wherein the storage device comprises:
a storage medium; and
a read/write head, wherein the first read head and the second read head are incorporated as part of the read/write head.
22. The system of claim 12 , wherein the system is implemented as part of an integrated circuit.
23. A hard disk drive, the hard disk drive comprising:
a disk platter including a number of tracks each storing servo data;
a head assembly disposed in relation to the disk platter, wherein the head assembly includes a first read head and a second read head;
a data processing system including:
a first sector address mark detection circuit operable to detect the location of a sector address mark in a first data set derived from a first read head and sampled at a sample rate;
a second sector address mark detection circuit operable to detect the location of the sector address mark in a second data set derived from a first read head and sampled at a sample rate;
an integer distance calculation circuit operable to calculate an integer number of periods of the sample rate within a difference between a location of the sector address mark in the first data set and a location of the sector address mark in the second data set.