IP Library Granted Patent US 8,897,289
Granted Patent B2
US 8,897,289 · App. 14/221,011 · Granted Nov 25, 2014

Node system and supervisory node

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Quick Facts
Patent No.
US 8,897,289
App. No.
14/221,011
Granted
Nov 25, 2014
Kind
B2
Abstract

A node system includes a first node, a second node, and a supervisory node which transmit frames while increasing or decreasing the cycle microtick count, and determines reduced cycle microtick counts by subtracting or adding a rate correction limit value from or to the cycle microtick count of the supervisory node when reception of the first frame transmitted by the first node stop and the cycle microtick count of the supervisory node when reception of the first and second frames stop.

Claims (66)

1. A node system having a plurality of nodes, comprising:

a first node configured to:

correct a first rate correction value such that one or more cycles of the plurality of nodes synchronize,

transmit a first frame based on the corrected first rate correction value when an absolute value of the first rate correction value is within a threshold, and

stop transmission of the first frame when the absolute value of the first rate correction value exceeds the threshold;

a second node configured to:

correct a second rate correction value such that one or more cycles of the plurality of nodes synchronize,

transmit a second frame based on the corrected second rate correction value when an absolute value of the second rate correction value is within the threshold, and

stop transmission of the second frame when the absolute value of the second rate correction value exceeds the threshold; and

a third node configured to:

transmit a third frame while increasing or decreasing a clock cycle count, and

determine a reduced clock cycle count based on subtracting or adding the threshold value from or to the clock cycle count of the third node when transmission of the first and second frames stop.

2. The node system according to claim 1 , wherein each node of the plurality of nodes comprises:

a clock generator, and

a communication controller configured to:

transmit a frame in a slot assigned based on a clock cycle count generated every time the clock generator generates a first certain number of clocks in a continuously repeated cycle, and

manage an initial value of a clock cycle count corresponding to a cycle length of the cycle and a rate correction value for the initial value.

3. The node system according to claim 2 , wherein, for each pair of continuous cycles, the third node is configured to:

delay or advance an end of a preceding cycle of the cycle pair by a certain count,

advance or delay an end of a later cycle of the cycle pair by the certain count, and

transmit the third frame while repeating the increase or decrease of the clock cycle count thereafter.

4. The node system according to claim 1 , wherein the third node is further configured to:

cause the first and second nodes to restart transmission of the first and second frames,

set an intermediate value of the reduced clock cycle count as a clock cycle count, and

repeatedly transmit the third frame.

5. The node system according to claim 4 , wherein the third node is configured to repeatedly transmit the third frame after causing the first and second nodes to restart transmission of the first and second frames.

6. The node system according to claim 4 , wherein the third node further sets the intermediate value as the clock cycle count after the transmission of the first and second frames stops, and is further configured to:

cause the first and second nodes to set the first and second rate correction values such that a cycle length thereof matches a cycle length of the third node; and

cause the first and second nodes to restart the transmission of the first and second frames.

7. The node system according to claim 4 , wherein the intermediate value is a fault-tolerant mid-point value generated by deleting a third certain number of data according to a number of the reduced clock cycle count in order from a maximum value to a minimum value of the reduced clock cycle count and deleting the third certain number of data from the minimum value to the maximum value, and rounding up or rounding off a mean value of a maximum value and a minimum value of remaining reduced clock cycle count.

8. The node system according to claim 4 , wherein the intermediate value is a value obtained by rounding up or off a mean value of the reduced clock cycle count.

9. The node system according to claim 1 , wherein the third node is configured to:

transmit the third frame while repeatedly correcting a third rate correction value such that one or more cycles of the plurality of nodes synchronize; and

determine the reduced clock cycle count when determination is made that each cycle length of the plurality of nodes is in a range of a certain width continuously for a certain number of times.

10. The node system of according to claim 1 , wherein the plurality of nodes are connected via a transmission line.

11. A node comprising:

a clock generator; and

a communication controller configured to:

receive first and second frames which are assigned on a basis of a count generated every time the clock generator generates a first certain number of clocks in repeated cycles,

transmit a third frame assigned based on the count, and

manage an initial value of a clock cycle count corresponding to a cycle length of each of the cycles and a rate correction value for the initial value, wherein

the third frame is transmitted while increasing or decreasing the clock cycle count, and a reduced clock cycle count is determined based on subtracting or adding a certain threshold value from or to the clock cycle count when reception of the first and second frames stop.

12. The node according to claim 11 , wherein the communication controller is further configured to:

cause a first and a second node to restart transmission of the first and second frames; and

set an intermediate value of the reduced clock cycle count as a clock cycle count of the third node, and repeatedly transmit the third frame.

13. The node according to claim 12 , wherein the node is connected via a transmission line to at least the first and the second node.

14. The node according to claim 11 , wherein the communication controller is further configured to:

for each cycle pair, delay or advance an end of a preceding cycle of the cycle pair by a certain count,

advance or delay an end of the later cycle of the cycle pair by the certain count, and

transmit the third frame while repeating an increase or decrease of the cycle clock count thereafter.

15. A synchronization method executed by a plurality of nodes, the method comprising:

correcting, by a first node of the plurality of nodes, a first rate correction value such that one or more cycles of the plurality of nodes synchronize;

transmitting a first frame associated with the first node based on the corrected first rate correction value when an absolute value of the first rate correction value is within a threshold;

stopping transmission of the first frame when the absolute value of the first rate correction value exceeds the threshold;

correcting, by a second node of the plurality of nodes, a second rate correction value such that one or more cycles of the plurality of nodes synchronize;

transmitting a second frame associated with the second node based on the corrected second rate correction value when the absolute value of the second rate correction value is within the threshold;

stopping transmission of the second frame when the absolute value of the second rate correction value exceeds the threshold;

transmitting, by the third node, a third frame while increasing or decreasing a clock cycle count; and

determining a reduced clock cycle count based on subtracting or adding the threshold from or to the clock cycle count of the third node when transmission of the first and second frames stop.

16. The synchronization method according to claim 15 , further comprising:

transmitting, by each of the plurality of nodes, a frame in a slot assigned on a basis of a count generated when a certain number of clocks are generated in a repeated cycle; and

determining an initial value of the clock cycle count corresponding to a cycle length of each of the cycles and a rate correction value for the initial value.

17. The synchronization method according to claim 15 , further comprising:

causing the first and second nodes to restart transmission of the first and second frames;

setting an intermediate value for the reduced clock cycle count as the clock cycle count; and

repeatedly transmitting the third frame.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2014
From: SUINA, KENJI; ARAI, TAKASHI; MITA, KOICHI; SHIMAMURA, AKIRA; ISHIKAWA, HIDETOSHI; MORIYA, TAKASHI; NOZAWA, YUUKI; KONDO, HIDEKI
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 033613/0229 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2014
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 033613/0243 →