SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INFORMATION CONCURRENTLY IN MULTIPLE SCENARIOS TO REDUCE TOTAL POWER WITHIN A CIRCUIT DESIGN
A system is described that analyzes timing of a design and conditionally replaces values of a cell to lower total power within circuit paths having a positive timing margin. The system includes a computing device that includes a memory for storing modules and a processor that is operable to execute the modules. The modules cause the processor to conditionally replace a first semiconductor characteristic with a second semiconductor characteristic associated with a cell in a path of a circuit design and estimating a delay and a slack of the path based upon the first semiconductor characteristic. The modules also cause the processor to determine whether the second semiconductor characteristic causes a timing violation with respect to the path and causes conditional replacement of the second semiconductor characteristic with a third semiconductor characteristic until the timing violation is removed.
1 . An apparatus comprising:
a computing device, the computing device comprising:
a memory operable to store one or more modules;
a processor coupled to the memory, the processor operable to execute the one or more modules to:
cause the processor to conditionally replace a first semiconductor characteristic with a second semiconductor characteristic associated with at least one cell in at least one path in a circuit design and estimating a delay and a slack of the at least one path based upon the first characteristic semiconductor characteristic; and
cause the processor to determine whether the second semiconductor characteristic causes a timing violation with respect to the at least one path and causing conditional replacement of the second semiconductor characteristic with a third semiconductor characteristic until the timing violation is removed.
2 . The apparatus as recited in claim 1 , wherein first semiconductor characteristic comprises at least one of a first channel length characteristic, a first voltage threshold implant, or a first cell size characteristic, the second semiconductor characteristic comprises at least one of a second channel length characteristic, a second voltage threshold implant, or a second cell size characteristic, and the third semiconductor characteristic comprises at least one of a third channel length characteristic, a third voltage threshold implant, or a third cell size characteristic.
3 . The apparatus as recited in claim 1 , wherein the at least one cell having the second semiconductor characteristic has an equivalent footprint area as the at least one cell having the first characteristic semiconductor characteristic.
4 . The apparatus as recited in claim 1 , wherein the processor is further operable to execute the one or more modules to exempt clock network cells and cells having transition or capacitance violations from the conditional replacement.
5 . The apparatus as recited in claim 1 , wherein the processor is further operable to execute the one or more modules to conditionally replace the second semiconductor characteristic with a third semiconductor characteristic with respect to a minimum number of cells to remove the timing violation.
6 . The apparatus as recited in claim 1 , wherein the at least one cell having the second semiconductor characteristic has a smaller footprint area as the at least one cell having the first characteristic semiconductor characteristic.
7 . The apparatus as recited in claim 1 , wherein the processor is further operable to execute the iteratively replace the second semiconductor characteristic with a third semiconductor characteristic to remove the timing violation.
8 . A method comprising:
conditionally replacing a first semiconductor characteristic with a second semiconductor characteristic associated with at least one cell in at least one path in a circuit design;
estimating a delay and a slack of the at least one path based on the conditional replacement;
determining whether the conditional replacement causes a timing violation with respect to the at least one path; and
conditionally replacing the second semiconductor characteristic associated with the at least one cell with a third semiconductor characteristic until the timing violation is removed.
9 . The method as recited in claim 8 , wherein first semiconductor characteristic comprises at least one of a first channel length characteristic, a first voltage threshold implant, or a first cell size characteristic, the second semiconductor characteristic comprises at least one of a second channel length characteristic, a second voltage threshold implant, or a second cell size characteristic, and the third semiconductor characteristic comprises at least one of a third channel length characteristic, a third voltage threshold implant, or a third cell size characteristic.
10 . The method as recited in claim 8 , wherein the at least one cell having the second semiconductor characteristic has an equivalent footprint area as the at least one cell having the first semiconductor characteristic.
11 . The method as recited in claim 8 , further comprising exempting clock network cells and cells having transition or capacitance violations from the conditional replacement.
12 . The method as recited in claim 8 , conditionally replacing the second semiconductor characteristic with a third semiconductor characteristic with respect to a minimum number of cells to remove the timing violation.
13 . The method as recited in claim 8 , wherein the at least one cell having the second semiconductor characteristic has a smaller footprint area as the at least one cell having the first characteristic semiconductor characteristic.
14 . The method as recited in claim 8 , further comprising iteratively replace the second semiconductor characteristic with a third semiconductor characteristic to remove the timing violation.
15 . An apparatus comprising:
a computing device, the computing device comprising:
a memory operable to store one or more modules;
a processor coupled to the memory, the processor operable to execute the one or more modules to:
receive an input file, the input file including data representing a circuit design, the circuit design including at least one cell;
cause the processor to conditionally replace a first semiconductor characteristic with a second semiconductor characteristic associated with the at least one cell in at least one path in the circuit design and estimating a delay and a slack of the at least one path based upon the first semiconductor characteristic; and
cause the processor to determine whether the second semiconductor characteristic causes a timing violation with respect to the at least one path and causing conditional replacement of the second semiconductor characteristic with a third semiconductor characteristic until the timing violation is removed.
16 . The apparatus as recited in claim 15 , wherein first semiconductor characteristic comprises at least one of a first channel length characteristic, a first voltage threshold implant, or a first cell size characteristic, the second semiconductor characteristic comprises at least one of a second channel length characteristic, a second voltage threshold implant, or a second cell size characteristic, and the third semiconductor characteristic comprises at least one of a third channel length characteristic, a third voltage threshold implant, or a third cell size characteristic.
17 . The apparatus as recited in claim 15 , wherein the at least one cell having the second semiconductor characteristic has an equivalent footprint area as the at least one cell having the first semiconductor characteristic.
18 . The apparatus as recited in claim 15 , wherein the processor is further operable to execute the one or more modules to exempt clock network cells and cells having transition or capacitance violations from the conditional replacement.
19 . The apparatus as recited in claim 15 , wherein the processor is further operable to execute the one or more modules to conditionally replace the second semiconductor characteristic with a third semiconductor characteristic with respect to a minimum number of cells to remove the timing violation.
20 . The apparatus as recited in claim 15 , wherein the at least one cell having the second semiconductor characteristic has an equivalent footprint area as the at least one cell having the first semiconductor characteristic.