DSP SerDes receiver with FFE-DFE-DFFE data path
A SerDes receiver device can receive binary signals via wireline channel such that information recovery is primarily or entirely performed via DSP algorithms in the digital domain includes an analog to digital converter, adaptation and calibration blocks, and a sequential n-way parallel equalization data path. The data path provides preliminary equalization of digital input symbols through a feed forward equalizer block followed by a decision feedback equalizer block, to which a k-slice decision feed forward equalizer block is appended for generating equalized hard decision outputs. The decision feed forward equalizer block may include a concatenation of cascading DFFE slices to improve the performance of the data path.
1. A system for generating digital data from a received analog signal, comprising:
an analog to digital converter configured to generate at least one input symbol from the received analog signal;
at least one preliminary equalizer block including
a feed forward equalizer configured to generate at least one first output symbol from the at least one input symbol by applying feed forward equalization to the at least one input symbol; and
a decision feedback equalizer configured to generate at least one first hard decision from the at least one first output symbol by applying decision feedback equalization to the at least one first output symbol; and
at least one decision feed forward (DFF) equalizer block including
a latency matching block configured to generate at least one latency matched input symbol by setting a first delay of the at least one input symbol generated by the analog to digital converter;
a product block configured to generate a product of at least one coefficient and the at least one first hard decision;
a result block configured to generate at least one final output symbol by combining the product with the at least one latency matched input symbol; and
a decision device configured to generate at least one second hard decision based on the at least one final output symbol.
2. The system of claim 1 , further comprising:
a calibration block operably coupled to the analog to digital converter and configured to correct at least one of a gain mismatch, an offset mismatch, and a time error; and
an adaptation block configured to adjust a coefficient of at least one of the feed forward equalizer, the decision feedback equalizer, and the decision feed forward equalizer.
3. The system of claim 1 , wherein
the product block is a multiplier configured to multiply the at least one first hard decision by at least one coefficient to approximate inter-symbol interference for the reconstructed analog signal; and
the result block is a combiner configured to subtract the approximate inter-symbol interference from the at least one latency matched input symbol.
4. The system of claim 1 , wherein the decision device is at least one of a comparator or a slicer.
5. The system of claim 1 , wherein at least one of the feed forward equalizer, the decision feedback equalizer, and the decision feed forward equalizer is an N-way parallel filter, where N is a positive integer.
6. The system of claim 1 , wherein at least one DFF equalizer block is a subsequent DFF equalizer block including
a subsequent latency matching block configured to generate at least one subsequent latency matched input symbol by setting at least (i) a first delay of the at least one input symbol from the analog to digital converter and (ii) at least one subsequent delay of a hard decision generated by a prior DFF equalizer block;
a subsequent product block configured to generate at least one subsequent product of the hard decision and at least one coefficient;
a subsequent result block configured to generate at least one subsequent final output symbol by combining the subsequent product with the at least one subsequent latency matched input symbol; and
a subsequent decision device configured to generate at least one subsequent hard decision based on the at least one subsequent final output symbol.
7. The system of claim 6 , wherein
the subsequent product block is a multiplier configured to multiply the at least one hard decision by at least one coefficient to approximate inter-symbol interference for the reconstructed analog signal; and
the subsequent result block is a combiner configured to subtract the approximate inter-symbol interference from the at least one subsequent latency matched input symbol.
8. The system of claim 1 , wherein the system is embodied in a serializer/deserializer (SerDes) receiver device.
9. A method for generating equalized digital data from a received analog signal, comprising:
generating at least one input symbol from the received analog signal via an analog to digital converter;
generating at least one first output symbol by applying feed forward equalization to the at least one input symbol;
generating at least one first hard decision by applying decision feedback equalization to the at least one first output symbol;
generating at least one latency matched input symbol by setting a first delay of the at least one input symbol generated by the analog to digital converter;
generating a product of the at least one first hard decision and at least one coefficient;
generating at least one final output symbol by combining the product with the at least one latency matched input symbol; and
generating via a decision device at least one second hard decision based on the at least one final output symbol.
10. The method of claim 9 , wherein the generating a product of the at least one first hard decision and at least one coefficient includes
multiplying the at least one first hard decision by at least one coefficient to approximate inter-symbol interference for the reconstructed analog signal.
11. The method of claim 9 , wherein the generating at least one final output symbol by combining the product with the at least one latency matched input symbol includes
generating at least one final output symbol by subtracting the approximate inter-symbol interference from the at least one latency matched input symbol.
12. The method of claim 9 , further comprising:
generating at least one subsequent latency matched input symbol by setting at least (i) a first delay of the at least one input symbol generated by the analog to digital converter and (ii) at least one subsequent delay of a hard decision generated by a prior DFF equalizer block;
generating at least one subsequent product of the at least one hard decision and at least one coefficient;
generating at least one subsequent final output symbol by combining the subsequent product with the at least one subsequent latency matched input symbol; and
generating at least one subsequent hard decision based on the at least one subsequent final output symbol.
13. The method of claim 12 , wherein the generating at least one subsequent product of the at least one hard decision and at least one coefficient includes
multiplying the at least one hard decision by at least one coefficient to approximate inter-symbol interference for the reconstructed analog signal.
14. The method of claim 12 , wherein the generating at least one subsequent final output symbol includes combining the subsequent product with the at least one subsequent latency matched input symbol to generate at least one subsequent final output symbol includes
generating at least one subsequent final output symbol by subtracting the approximate inter-symbol interference from the at least one latency matched input symbol.
15. The method of claim 12 , wherein the generating at least one subsequent hard decision based on the at least one subsequent final output symbol includes
generating at least one subsequent hard decision based on the at least one subsequent final output symbol via at least one of a comparator and a slicer.
16. The method of claim 9 , wherein the method is embodied in instructions executable by a processor operably coupled to a SerDes receiver.
17. A serializer/deserializer (SerDes) receiver device incorporating a system for generating digital data from a received analog signal, comprising:
an analog to digital converter configured to generate at least one input symbol from the received analog signal;
at least one preliminary equalizer block including
a feed forward equalizer configured to generate at least one first output symbol from the at least one input symbol by applying feed forward equalization to the at least one input symbol; and
a decision feedback equalizer configured to generate at least one first hard decision from the at least one first output symbol by applying decision feedback equalization to the at least one first output symbol; and
at least one decision feed forward (DFF) equalizer block including
a latency matching block configured to generate at least one latency matched input symbol by setting a first delay of the at least one input symbol generated by the analog to digital converter;
a product block configured to generate a product of at least one coefficient and the at least one first hard decision;
a result block configured to generate at least one final output symbol by combining the product with the at least one latency matched input symbol; and
a decision device configured to generate at least one second hard decision based on the at least one final output symbol.