Systems and methods for skew tolerant multi-head data processing
View Patent ↗Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for processing skew tolerant processing of data derived from multiple read heads.
1. A data processing system, the system comprising:
a buffer circuit operable to store a first set of digital samples derived from a first read head as a buffered data set;
a selector circuit operable to select one of the buffered data set or the first set of digital samples as a processing output; and
a joint equalizer circuit operable to apply a joint equalization algorithm to a combination of the processing output and a second set of digital samples derived from a second read head to yield an equalized output.
2. The data processing system of claim 1 , wherein the data processing system is implemented as part of a storage device, wherein the storage device includes a storage medium having at least a first track located at a radius from a center of the storage medium, wherein the first read head is disposed at least partially over the first track, and wherein selection between the buffered data set and the first set of digital samples is based at least in part on the radius.
3. The data processing system of claim 2 , wherein when the radius indicates a location near the center of the storage medium the buffered data set is selected as the processing output, and wherein when the radius indicates a location near an outer edge of the storage medium the first set of digital samples is selected as the processing output.
4. The data processing system of claim 2 , wherein the buffer circuit is large enough to store data from one full track near the center of the storage medium, and is not large enough to store data from one full track near an outer edge of the storage medium.
5. The data processing system of claim 1 , wherein the data processing system is implemented as part of a storage device, wherein the storage device includes a storage medium having at least a first track and a second track, and wherein when the first read head is disposed over the first track and the second read head is disposed over the second track, the processing output is selected as the buffered data set.
6. The data processing system of claim 5 , wherein the buffered data set corresponds to data derived by the first read head during a prior rotation of the storage medium when the first read head was disposed over the second track.
7. The data processing system of claim 1 , wherein the data processing system is implemented as part of a storage device, wherein the storage device includes a storage medium having at least a first track and a second track, and wherein when both the first read head is disposed over the first track and the second read head is disposed over the first track, the processing output is selected as the first set of digital samples.
8. The data processing system of claim 1 , wherein the joint equalizer circuit is a first joint equalizer circuit having a target corresponding to the second set of digital samples, the system comprising:
a second joint equalizer circuit operable to apply a joint equalization algorithm to the combination of the processing output and the second set of digital samples, wherein the second joint equalizer circuit has a target corresponding to the first set of digital samples.
9. The data processing system of claim 8 , wherein the data processing system is implemented as part of a storage device, wherein the storage device includes a storage medium having at least a first track located at a radius from a center of the storage medium and a second track, and wherein selection between the buffered data set and the first set of digital samples is based at least in part on the radius.
10. The data processing system of claim 9 , the system further comprising:
a controller circuit operable to disable the second joint equalizer circuit based at least in part on the radius.
11. The data processing system of claim 10 , wherein the controller circuit disables the second joint equalizer circuit when the radius indicates a location where the first read head is disposed over the first track and the second read head is disposed partially over both the first track and the second track.
12. The data processing system of claim 1 , wherein the data processing system is implemented as part of an integrated circuit.
13. A method for data processing, the method comprising:
receiving a first set of digital samples derived from a first read head;
receiving a second set of digital samples derived from a second read head;
buffering the first set of digital samples as a buffered data set;
selecting one of the buffered data set or the first set of digital samples as a processing output; and
applying a joint equalization algorithm using a joint equalizer circuit to a combination of the processing output and a second set of digital samples derived from a second read head to yield an equalized output.
14. The method of claim 13 , wherein the method further comprises:
providing a storage medium having at least a first track located at a radius from a center of the storage medium, wherein the first read head is disposed at least partially over the first track, and wherein selection between the buffered data set and the first set of digital samples is based at least in part on the radius.
15. The method of claim 14 , wherein when the radius indicates a location near the center of the storage medium the buffered data set is selected as the processing output, and wherein when the radius indicates a location near an outer edge of the storage medium the first set of digital samples is selected as the processing output.
16. The method of claim 14 , wherein the buffer circuit is large enough to store data from one full track near the center of the storage medium, and is not large enough to store data from one full track near an outer edge of the storage medium.
17. The method of claim 13 , wherein the method further comprises:
providing a storage medium having at least a first track and a second track, wherein when the first read head is disposed over the first track and the second read head is disposed over the second track, the processing output is selected as the buffered data set.
18. The method of claim 13 , wherein the joint equalizer circuit is a first joint equalizer circuit having a target corresponding to the second set of digital samples, the method further comprising:
applying the joint equalization algorithm using a second joint equalizer circuit to the combination of the processing output and the second set of digital samples to yield a second equalized output, wherein the second joint equalizer circuit has a target corresponding to the first set of digital samples.
19. The method of claim 18 , wherein the method further comprises:
providing a storage medium having at least a first track located at a radius from a center of the storage medium and a second track, and wherein selection between the buffered data set and the first set of digital samples is based at least in part on the radius.
20. The method of claim 19 , wherein the method further comprises:
disabling the second joint equalizer circuit based at least in part on the radius.