Frequency division

1. A frequency divider comprising:

a signal generation stage arranged to employ a clock signal at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal;

a synchronization stage arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal; and

a mode control stage coupled to the signal generation stage for generating a selection signal indicative of the completion of each cycle of the first reference signal, and wherein the switching between the first reference signal and the second reference signal is responsive to the selection signal.

2. A frequency divider as claimed in claim 1 , wherein the mode control stage comprises a divide-by-two stage for generating the selection signal having a frequency equal to half of a frequency of the first reference signal.

3. A frequency divider as claimed in claim 1 , wherein the signal generation stage comprises a division stage for generating the first reference signal by dividing the clock signal by an integer division ratio.

4. A frequency divider as claimed in claim 3 , wherein the division stage is arranged to alternately increase and decrease the integer division ratio in response to the selection signal.

5. A frequency divider as claimed in claim 4 , wherein the division stage comprises:

a clocked delay line having a plurality of delay stages coupled in series;

a feedback controller coupled between an input of the clocked delay line and outputs of one or more of the delay stages and arranged to provide a periodic input signal to the input of the clocked delay line, wherein each period of the input signal is dependent on signals at respective outputs of the one or more of the delay stages;

an output of the clocked delay line coupled to an output of one of the delay stages for delivering the first reference signal; and

a delay circuit coupled to the one, or another, of the delay stages for generating the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal;

wherein the feedback controller is arranged to alternately increase and decrease the integer division ratio in response to the selection signal by selecting the one or more of the delay stages from the plurality of delay stages.

6. A frequency divider as claimed in claim 4 , wherein the division stage comprises:

a clocked delay line having a plurality of delay stages coupled in series, wherein the delay stages occupying odd numbered positions in the clocked delay line are arranged to be clocked by the clock signal and the delay stages occupying even numbered positions in the clocked delay line are arranged to be clocked by an inverse clock signal corresponding to an inversion of the clock signal;

a feedback controller coupled between an input of the clocked delay line and outputs of one or more of the delay stages and arranged to provide a periodic input signal to the input of the clocked delay line, wherein each period of the input signal is dependent on signals at respective outputs of the one or more of the delay stages;

a first output of the clocked delay line coupled to an output of one of the delay stages for delivering the first reference signal; and

a second output of the clocked delay line coupled to another one of the delay stages for delivering the second reference signal;

wherein the feedback controller is arranged to alternately increase and decrease the integer division ratio in response to the selection signal by selecting the one or more of the delay stages from the plurality of delay stages.

7. A frequency divider as claimed in claim 6 , wherein each of the delay stages comprises a tri-state inverter circuit.

8. A frequency divider as claimed in claim 4 , wherein the alternate increase and decrease of the integer division ratio in response to the selection signal is an alternate increase and decrease of the integer division ratio by unity.

9. A frequency divider as claimed in claim 5 , the feedback controller comprising:

a first pair of switches comprising a first controller switch and a second controller switch coupled in parallel, a second pair of switches comprising a third controller switch and a fourth controller switch coupled in parallel, a third pair of switches comprising a fifth controller switch and a sixth controller switch coupled in parallel, and a fourth pair of switches comprising a seventh controller switch and an eighth controller switch coupled in parallel, wherein the first and second pairs of switches are coupled in a series arrangement between a first voltage rail and the input of the clocked delay line, and the third and fourth pairs of switches are coupled in a series arrangement between a second voltage rail and the input of the clocked delay line;

wherein at least one of the first, third, fifth and seventh controller switches are arranged to be switched dependent on a required division ratio of the division stage; and

wherein the second, fourth, sixth and eighth controller switches are arranged to be switched dependent on respective outputs of respective delay stages of the clocked delay line.

10. A frequency divider as claimed in claim 9 , wherein the first, second, third and fourth controller switches comprise n-channel metal oxide silicon, NMOS, transistors and the fifth, sixth, seventh and eighth controller switches comprise p-channel metal oxide silicon, PMOS, transistors.

11. A frequency divider as claimed in claim 4 , the synchronization stage comprising:

first, third and fifth synchronization switches coupled in a series arrangement between a/the first voltage rail and the output of the frequency divider;

second, fourth and sixth synchronization switches coupled in a series arrangement between the first voltage rail and the output of the frequency divider;

seventh, ninth and eleventh synchronization switches coupled in a series arrangement between the output of the frequency divider and a/the second voltage rail;

eighth, tenth and twelfth synchronization switches coupled in a series arrangement between the output of the frequency divider and the second voltage rail;

wherein, in a first state:

the first and twelfth switches are switched in response to the selection signal;

the second and eleventh synchronization switches are switched in response to an inverse of the selection signal;

the third and tenth synchronization switches are switched in response to the clock signal;

the fourth and ninth synchronization switches are switched in response to the inverse clock signal;

the fifth and seventh synchronization switches are switched in response to the first reference signal; and

the sixth and eighth synchronization switches are switched in response to the second reference signal.

12. A frequency divider as claimed in claim 11 , wherein, in a second state:

the second and eleventh switches are switched in response to the selection signal;

the first and twelfth synchronization switches are switched in response to an inverse of the selection signal;

the third, ninth and tenth synchronization switches are switched in response to the clock signal;

the fourth synchronization switch is switched in response to the inverse clock signal;

the fifth, sixth and eighth synchronization switches are switched in response to the first reference signal; and

the seventh synchronization switch is switched in response to the second reference signal.

13. A frequency divider as claimed in claim 11 , wherein, in a second state:

the first and twelfth synchronization switches are switched in response to the selection signal;

the second and eleventh switches are switched in response to an inverse of the selection signal;

the fourth synchronization switch is switched in response to the clock signal;

the third, ninth and tenth synchronization switches are switched in response to the inverse clock signal;

the seventh synchronization switch is switched in response to the first reference signal; and

the fifth, sixth and eighth synchronization switches are switched in response to the second reference signal.

14. A frequency divider as claimed in claim 11 , wherein the first, second, third, fourth, fifth and sixth synchronization switches comprise n-channel metal oxide silicon, NMOS, transistors and the seventh, eighth, ninth, tenth, eleventh and twelfth synchronization switches comprise p-channel metal oxide silicon, PMOS, transistors.

15. A frequency synthesizer comprising:

a frequency divider comprising:

a signal generation stage arranged to employ a clock signal at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal;

a synchronization stage arranged to

generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal portion and the second reference signal once per cycle of the output signal; and

a mode control stage coupled to the signal generation stage for generating a selection signal indicative of the completion of each cycle of the first reference signal, and wherein the switching between the first reference signal and the second reference signal is responsive to the selection signal.

16. A wireless communication apparatus comprising:

a frequency divider comprising:

a signal generation stage arranged to employ a clock signal at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal;

a synchronization stage arranged to

generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal; and

a mode control stage coupled to the signal generation stage for generating a selection signal indicative of the completion of each cycle of the first reference signal, and wherein the switching between the first reference signal and the second reference signal is responsive to the selection signal.

17. A method of frequency division comprising:

employing a clock signal at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal;

generating an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal; and

generating a selection signal indicative of the completion of each cycle of the first reference signal, and wherein the switching between the first reference signal and the second reference signal is responsive to the selection signal.

18. A frequency divider comprising:

a signal generation stage arranged to employ a clock signal at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal; and

a synchronization stage arranged to:

generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal;

a mode control stage coupled to an output of the frequency divider for generating a selection signal indicative of the completion of each cycle of the output signal and comprising a divide-by-two stage for generating the selection signal having a frequency equal to half of the output frequency, and wherein the switching between the first reference signal and the second reference signal is responsive to the selection signal; and

wherein:

the first reference signal is the clock signal;

the synchronization stage is arranged to generate an intermediate signal by switching between the first reference signal and the second reference signal once per cycle of the output signal; and

the synchronization stage comprises a division stage for generating the output signal by dividing the intermediate signal by an integer division ratio.

19. A frequency divider comprising:

a signal generation stage arranged to employ a clock signal at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal; and

a synchronization stage arranged to:

generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal;

a mode control stage coupled to an output of the frequency divider for generating a selection signal indicative of the completion of each cycle of the output signal and comprising a divide-by-two stage for generating the selection signal having a frequency equal to half of the output frequency, and wherein the switching between the first reference signal and the second reference signal is responsive to the selection signal; and

wherein the synchronization stage comprises a first tri-state inverter for selecting the first reference signal, a second tri-state inverter for selecting the second reference signal, a third tri-state inverter for synchronizing the selecting of the first reference signal to a transition of the clock signal, and a fourth tri-state inverter for synchronizing the selecting of the second reference signal to an opposite of the clock signal.