Read disturb handling in NAND flash
An apparatus having a processor and an interface to a nonvolatile memory having a plurality of blocks is disclosed. The processor is configured to (i) monitor a number of reads since a respective erase in at least one of the blocks in the nonvolatile memory, (ii) move a page from a first block to a second block in response to the number of reads exceeding a first threshold where the first block is partially programmed and (iii) move the page from the first block to the second block in response to the number of reads exceeding a second threshold where the first block is fully programmed. The first threshold is less than the second threshold.
1. An apparatus comprising:
an interface to a nonvolatile memory having a plurality of blocks; and
a processor configured to (i) monitor a number of reads since a respective erase in at least one of said blocks in said nonvolatile memory, (ii) move a page from a first block to a second block in response to said number of reads exceeding a first threshold where said first block is partially programmed and (iii) move said page from said first block to said second block in response to said number of reads exceeding a second threshold where said first block is fully programmed, wherein said first threshold is less than said second threshold.
2. The apparatus according to claim 1 , wherein said second block is a most recently programmed block.
3. The apparatus according to claim 1 , wherein said second threshold is less than a third threshold that triggers a refresh of said first block.
4. The apparatus according to claim 1 , wherein said processor is further configured to flag said second block to receive future writes.
5. The apparatus according to claim 1 , wherein said processor is further configured to move another page from said first block to said second block in response to reading said other page after said move of said page.
6. The apparatus according to claim 1 , wherein said second block is in a different integrated circuit than said first block.
7. The apparatus according to claim 1 , where said processor is further configured to move said page from said first block to said second block in response to said number of reads exceeding a refresh threshold.
8. The apparatus according to claim 1 , wherein said nonvolatile memory comprises NAND flash memory.
9. The apparatus according to claim 1 , wherein said processor forms part of a solid-state drive controller.
10. The apparatus according to claim 1 , wherein said apparatus is implemented as one or more integrated circuits.
11. A method for handling read disturb in a nonvolatile memory, comprising the steps of:
(A) monitoring a number of reads since a respective erase in at least one of a plurality of blocks in said nonvolatile memory;
(B) moving a page from a first block to a second block in response to said number of reads exceeding a first threshold where said first block is partially programmed; and
(C) moving said page from said first block to said second block in response to said number of reads exceeding a second threshold where said first block is fully programmed, wherein said first threshold is less than said second threshold.
12. The method according to claim 11 , wherein said second block is a most recently programmed block.
13. The method according to claim 11 , wherein said second threshold is less than a third threshold that triggers a refresh of said first block.
14. The method according to claim 11 , further comprising the step of:
flagging said second block to receive future writes.
15. The method according to claim 11 , further comprising the step of:
moving another page from said first block to said second block in response to reading said other page after said move of said page.
16. The method according to claim 11 , wherein said second block is in a different integrated circuit than said first block.
17. The method according to claim 11 , further comprising the step of:
moving said page from said first block to said second block in response to said number of reads exceeding a refresh threshold.
18. An apparatus comprising:
a nonvolatile memory having a plurality of blocks; and
a controller configured to (i) monitor a number of reads since a respective erase in at least one of said blocks in said nonvolatile memory, (ii) move a page from a first block to a second block in response to said number of reads exceeding a first threshold where said first block is partially programmed and (iii) move said page from said first block to said second block in response to said number of reads exceeding a second threshold where said first block is fully programmed, wherein said first threshold is less than said second threshold.