MIMO reception device and MIMO reception method
Provided are a MIMO transmission device and a MIMO transmission method which can improve reception quality of a response signal. A terminal ( 100 ) as the MIMO transmission device maps a first and a second element of the ACK/NACK signal vector formed from ACK/NACK signals onto a first and a second stream, respectively, and transmits the elements contained in a 2SC-FDMA symbol in a single slot. In the terminal ( 100 ), a response signal vector formation unit ( 140 ) forms [a·S ack , 0] as the ACK/NACK signal vector in a first SC-FDMA symbol and [0, a·S ack ] as an ACK/NACK signal vector in a second SC-FDMA symbol. A precoding unit ( 165 ) uses a unitary matrix to precode the ACK/NACK signal vector formed in the response signal vector formation unit ( 140 ).
1. An integrated circuit for controlling a process comprising:
forming a plurality of ACK/NACK signal vectors based on a signal indicative of ACK/NACK, the plurality of ACK/NACK signal vectors including a first ACK/NACK signal vector and a second ACK/NACK signal vector different from the first ACK/NACK signal vector;
generating a first stream using a first sequence, the first ACK/NACK signal vector and the second ACK/NACK signal vector, and to generate a second stream using a second sequence different from the first sequence, the first ACK/NACK signal vector and the second ACK/NACK signal vector; and
transmitting the first stream and the second stream that are spatial-multiplexed.
2. The integrated circuit according to claim 1 , wherein a combination of elements included in the first ACK/NACK signal vector is different from a combination of elements included in the second ACK/NACK signal vector.
3. The integrated circuit according to claim 1 , wherein a phase of the first ACK/NACK signal vector is different from a phase of the second ACK/NACK signal vector.
4. The integrated circuit according to claim 1 , wherein each of the first ACK/NACK signal vector and the second ACK/NACK signal vector includes an element which is the same as said signal indicative of ACK/NACK and another element which is different from said signal indicative of ACK/NACK.
5. The integrated circuit according to claim 4 , wherein the other element is generated from said signal indicative of ACK/NACK.
6. The integrated circuit according to claim 1 , wherein the first ACK/NACK signal vector includes a first element and a second element, which are both the same as said signal indicative of ACK/NACK, and the second ACK/NACK signal vector includes a first element which is the same as said signal indicative of ACK/NACK and a second element which is generated from said signal indicative of ACK/NACK.
7. The integrated circuit according to claim 1 , wherein each of the first ACK/NACK signal vector and the second ACK/NACK signal vector includes a first element which is generated from said signal indicative of ACK/NACK and a second element which is not generated from said signal indicative of ACK/NACK.
8. The integrated circuit according to claim 1 , wherein the first ACK/NACK signal vector is mapped on a first symbol and the second ACK/NACK signal vector is mapped on a second symbol, the first and second symbols being included in one subframe.
9. The integrated circuit according to claim 8 , wherein, in said one subframe, the first symbol is a symbol immediately before a reference signal and the second symbol is a symbol immediately after the reference signal.
10. The integrated circuit according to claim 1 , wherein the first ACK/NACK signal vector and the second ACK/NACK signal vector are respectively mapped repeatedly on corresponding symbols in one subframe.
11. The integrated circuit according to claim 1 , wherein the first ACK/NACK signal vector and the second ACK/NACK signal vector are respectively replicated, and the replicated ACK/NACK signal vectors are transmitted on the first stream and the second stream by being spatial-multiplexed.
12. The integrated circuit according to claim 1 , wherein the first stream and the second stream do not include an element that is zero.
13. The integrated circuit according to claim 1 , wherein the first ACK/NACK signal vector is orthogonal to the second ACK/NACK signal vector.
14. The integrated circuit according to claim 1 , wherein the first ACK/NACK signal vector and the second ACK/NACK signal vector are mapped around a reference signal on each slot in one subframe.
15. The integrated circuit according to claim 1 , wherein the first ACK/NACK signal vector and the second ACK/NACK signal vector are mapped by overwriting data.
16. An integrated circuit for controlling a process comprising:
receiving a first stream and a second stream that are transmitted from a transmission apparatus and that are spatial-multiplexed, wherein, the first stream is generated using a first sequence, a first ACK/NACK signal vector and a second ACK/NACK signal vector different from the first ACK/NACK signal vector, and the second stream is generated using a second sequence different from the first sequence, the first ACK/NACK signal vector and the second ACK/NACK signal vector, each of the first ACK/NACK signal vector and the second ACK/NACK signal vector being formed based on a signal indicative of ACK/NACK; and
detecting said signal indicative of ACK/NACK based on the first ACK/NACK signal vector and the second ACK/NACK signal vector.
17. The integrated circuit according to claim 16 , wherein a combination of elements included in the first ACK/NACK signal vector is different from a combination of elements included in the second ACK/NACK signal vector.
18. The integrated circuit according to claim 16 , wherein a phase of the first ACK/NACK signal vector is different from a phase of the second ACK/NACK signal vector.
19. The integrated circuit according to claim 16 , wherein each of the first ACK/NACK signal vector and the second ACK/NACK signal vector includes an element which is the same as said signal indicative of ACK/NACK and another element which is different from said signal indicative of ACK/NACK.
20. The integrated circuit according to claim 19 , wherein the other element is generated from said signal indicative of ACK/NACK.
21. The integrated circuit according to claim 16 , wherein: the first ACK/NACK signal vector includes a first element and a second element, which are both the same as said signal indicative of ACK/NACK; and the second ACK/NACK signal vector includes a first element which is the same as said signal indicative of ACK/NACK and a second element which is generated from said signal indicative of ACK/NACK.
22. The integrated circuit according to claim 16 , wherein each of the first ACK/NACK signal vector and the second ACK/NACK signal vector includes a first element which is generated from said signal indicative of ACK/NACK and a second element which is not generated from said signal indicative of ACK/NACK.
23. The integrated circuit according to claim 16 , wherein the first ACK/NACK signal vector is mapped on a first symbol and the second ACK/NACK signal vector is mapped on a second symbol, the first and second symbols being included in one subframe.
24. The integrated circuit according to claim 23 , wherein, in said one subframe, the first symbol is a symbol immediately before a reference signal, and the second symbol is a symbol immediately after the reference signal.
25. The integrated circuit according to claim 16 , wherein the first ACK/NACK signal vector and the second ACK/NACK signal vector are respectively mapped on corresponding symbols in one subframe repeatedly.
26. The integrated circuit according to claim 16 , wherein the first ACK/NACK signal vector and the second ACK/NACK signal vector are respectively replicated, and the replicated ACK/NACK signal vectors are transmitted on the first stream and the second stream by being spatial-multiplexed.
27. The integrated circuit according to claim 16 , wherein the first stream and the second stream do not include an element that is zero.
28. The integrated circuit according to claim 16 , wherein the first ACK/NACK signal vector is orthogonal to the second ACK/NACK signal vector.
29. The integrated circuit according to claim 16 , wherein the first ACK/NACK signal vector and the second ACK/NACK signal vector are mapped around a reference signal on each slot in one subframe.
30. The integrated circuit according to claim 16 , wherein the first ACK/NACK signal vector and the second ACK/NACK signal vector are mapped by overwriting data.