Logic gate array
View Patent ↗A logic gate array includes a substrate; an array of first conductive lines with plurality of first pads disposed on each of the first conductive lines on the substrate wherein the array of first conductive lines is disposed in a first direction; an array of isolation lines over the first conductive lines wherein the isolation lines are not disposed on the first pads; an array of second conductive lines with plurality of second pads disposed on each of the second conductive lines on the substrate wherein the array of first conductive lines is disposed in a second direction and wherein orientation of the second direction is oriented is different than the orientation of the first direction; and conductive ink dots printed on at least some of the intersection of the first conductive lines and the second conductive lines by connecting the corresponding first pads and corresponding second pads.
1. A logic gate array, comprising:
a substrate;
an array of first conductive lines with a plurality of first pads disposed on each of the first conductive lines, wherein the array of first conductive lines is disposed on the substrate in a first direction;
an array of isolation lines extending in a second direction over the first conductive lines, wherein the isolation lines are not disposed on the first pads, and wherein orientation of the second direction is different than the orientation of the first direction;
an array of second conductive lines with a plurality of second pads disposed on each of the second conductive lines, wherein the array of second conductive lines is disposed on the substrate in the second direction, and wherein each isolation line of the array of isolation lines bands only the geometry of a corresponding second conductive line of the array of second conductive lines; and
conductive ink dots that sufficiently cover the intersection of selected first pads and selected second pads to electrically connect the corresponding first conductive lines and the second conductive lines to enable logic circuitry of the logic gate array.
2. The logic gate array of claim 1 wherein the first direction is vertical direction and the second direction is horizontal direction.
3. The logic gate array of claim 1 wherein the first direction is horizontal direction and the second direction is vertical direction.
4. The logic gate array of claim 1 wherein the first conductive lines are connected to logical gates and the second conductive lines are connected to electrical signals.
5. The logic gate array of claim 4 wherein the logical gates are selected from a group comprising at least AND, OR, NOT, NAND, NOR, XOR gates or a combinations thereof.
6. The logic gate array of claim 1 wherein the second conductive lines are connected to logical gates and the first conductive lines are connected to electrical signals.
7. The logic gate array of claim 6 wherein the logical gates are selected from a group comprising at least AND, OR, NOT, NAND, NOR, XOR gates or a combinations thereof.
8. The logic gate array of claim 1 wherein the conductive ink is deposited with inkjet printing.
9. The logic gate array of claim 1 wherein orientation of the first conductive lines is essentially perpendicular to orientation of the second conductive lines.