Granted Patent B1

US 9,111,573 · App. 14/248,943 · Granted Aug 18, 2015

Inventors: Siva Swaroop Vontela (Longmont, CO); Scott M. Dziak (Fort Collins, CO)

Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.

G11B20/10046G11B20/1217G11B2020/1238

Abstract

Claims (55)

1. A method, comprising:

receiving a plurality of samples by a long filter and a short filter;

performing short filter operations on the plurality of samples by the short filter;

performing long filter operations on the plurality of samples by the long filter;

receiving short filter outputs from the short filter;

receiving long filter outputs from the long filter;

receiving information from a zero phase start module, the information including a target phase constraint, a polyant, and a zero phase start phase;

selecting two samples per preamble cycle of the short filter outputs and the long filter outputs based on the target phase constraint, the polyant, and the zero phase start phase;

decimating the short filter outputs and the long filter outputs such that the selected two samples for each of the long filter and the short filer per preamble cycle are output upon decimation; and

performing a sign comparison on the corresponding short filter and long filter outputs after decimation, wherein a sign mismatch of the corresponding short filter and long filter outputs indicates an end of a preamble.

2. The method of claim 1 , further comprising:

detecting the end of the preamble without interpolation.

3. The method of claim 1 , wherein the polyant is a quadrant, and wherein the preamble is implemented as a 4T preamble.

4. The method of claim 3 , wherein decimating the short filter outputs and the long filter outputs such that the selected two samples for each of the long filter and the short filter per preamble cycle are output upon decimation further comprises:

decimating, by a factor of 2, the short filter outputs and the long filter outputs such that the selected two samples for each of the long filter and the short filter per preamble cycle are output upon decimation.

5. The method of claim 1 , wherein the polyant is a hexant, and wherein the preamble is implemented as a 6T preamble.

6. The method of claim 5 , wherein decimating the short filter outputs and the long filter outputs such that the selected two samples for each of the long filter and the short filter per preamble cycle are output upon decimation further comprises:

decimating, by a factor of 3, the short filter outputs and the long filter outputs such that the selected two samples for each of the long filter and the short filter per preamble cycle are output upon decimation.

7. The method of claim 1 , wherein the selected samples per preamble cycle include two samples from the short filter and two samples from the long filter.

8. The method of claim 1 , wherein the long filter and the short filter have a same magnitude response and a same phase response at an NT preamble frequency.

9. The method of claim 1 , wherein the selected two samples for each of the long filter and the short filter per preamble cycle have a higher noise margin value than an average noise margin value of unselected samples per preamble cycle.

10. The method of claim 1 , further comprising:

predicting a phase of the short filter outputs and the long filter outputs based on the target phase constraint, the polyant, and the zero phase start phase.

11. A storage system, comprising:

a short filter, wherein the short filter is configured to receive a plurality of samples and perform short filter operations on the plurality of samples;

a long filter wherein the long filter is configured to receive a plurality of samples and perform long filter operations on the plurality of samples;

a zero phase start module configured to provide information including a target phase constraint, a polyant, and a zero phase start phase;

at least one decimator, the at least one decimator being communicatively coupled to the short filter, the long filter, the zero phase start module, and a comparator, wherein the at least one decimator is configured to:

receive short filter outputs from the short filter;

receive long filter outputs from the long filter;

receive information from the zero phase start module, the information including the target phase constraint, the polyant, and the zero phase start phase;

select two samples for each of the short filter outputs and long filter outputs per preamble cycle based on the target phase constraint, the polyant, and the zero phase start phase; and

decimate the short filter outputs and the long filter outputs such that the selected two samples per filter per preamble cycle are output upon decimation; and

the comparator, wherein the comparator is configured to:

perform a sign comparison on the corresponding short filter and long filter outputs after decimation, wherein a sign mismatch of the corresponding short filter and long filter outputs indicates an end of a preamble.

12. The storage system of claim 11 , wherein the end of the preamble is detected without interpolation.

13. The storage system of claim 11 , wherein the storage system is implemented as a RAID (redundant array of independent storage devices) system.

14. The storage system of claim 11 , wherein the storage system comprises at least one hard disk drive.

15. The storage system of claim 11 , wherein the selected two samples for each of the long filter and the short filter per preamble cycle have a higher noise margin value than an average noise margin value of unselected samples per preamble cycle.

16. A circuit, comprising:

at least one decimator, wherein the at least one decimator is configured to:

receive short filter outputs from a short filter;

receive long filter outputs from a long filter;

receive information from a zero phase start module, the information including a target phase constraint, a polyant, and a zero phase start phase;

select two samples per preamble cycle of the short filter outputs and the long filter outputs based on the target phase constraint, the polyant, and the zero phase start phase; and

decimate the short filter outputs and the long filter outputs such that the selected two samples for each of the long filter and the short filter per preamble cycle are output upon decimation; and

a comparator, wherein the comparator is configured to:

perform a sign comparison on the corresponding short filter and long filter outputs after decimation, wherein a sign mismatch of the corresponding short filter and long filter outputs indicates an end of a preamble.

17. The circuit of claim 16 , further comprising:

the short filter, wherein the short filter is configured to receive a plurality of samples and perform short filter operations on the plurality of samples;

the long filter, wherein the long filter is configured to receive a plurality of samples and perform long filter operations on the plurality of samples; and

the zero phase start module, wherein the zero phase start module is configured to provide information including the target phase constraint, the polyant, and the zero phase start phase.

18. The circuit of claim 16 , wherein the circuit comprises an integrated circuit implemented as at least one of a read channel, a read-write channel, a multi-sensor channel, data signal processing circuitry, or a communication channel.

19. The circuit of claim 16 , wherein the end of the preamble is detected without interpolation.

20. The circuit of claim 16 , wherein the selected two samples for each of the long filter and the short filter per preamble cycle have a higher noise margin value than an average noise margin value of unselected samples per preamble cycle.

Assignments (10)

Continuity (1)