IP Library Granted Patent US 8,976,476
Granted Patent B1
US 8,976,476 · App. 14/250,587 · Granted Mar 10, 2015

Storage device with read channel circuitry configured to provide continuity protection for subsector stitching

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Quick Facts
Patent No.
US 8,976,476
App. No.
14/250,587
Granted
Mar 10, 2015
Kind
B1
Abstract

A hard disk drive or other storage device comprises a storage medium, a read/write head, and read channel circuitry coupled to the read/write head. The read channel circuitry comprises a despreader configured to generate a stitched logic sector by stitching together subsectors of that logic sector that were interleaved with subsectors of other logic sectors for storage on the storage medium, and a subsector bridging control module configured to control a number of bridging bits inserted by the despreader between a given pair of adjacent subsectors of the stitched logic sector. The subsector bridging control module may be illustratively configured to cause the despreader to insert a sufficient number of bridging bits between each pair of adjacent subsectors of the stitched logic sector so as to prevent discontinuities that might otherwise arise from use of X-averaging in generation of Y samples from X samples in a retry mode of operation.

Claims (36)

1. An apparatus comprising:

read channel circuitry adapted for coupling to a read/write head of a storage device;

wherein the read channel circuitry comprises:

a despreader configured to generate a stitched logic sector by stitching together subsectors of that logic sector that were interleaved with subsectors of other logic sectors for storage on a storage medium of the storage device; and

a subsector bridging control module associated with the despreader and configured to control a number of bridging bits inserted by the despreader between a given pair of adjacent subsectors of the stitched logic sector.

2. The apparatus of claim 1 wherein the read channel circuitry further comprises:

analog frontend circuitry configured to receive an analog read signal from the read/write head via a preamplifier of the storage device;

an analog-to-digital converter configured to convert the analog read signal to a digital read signal; and

digital finite impulse response (DFIR) filter circuitry comprising at least one DFIR filter configured to process X samples of the digital read signal to generate Y samples.

3. The apparatus of claim 1 wherein the stitched logic sector comprises X samples that are provided to a DFIR filter for use in generating Y samples in a retry mode of operation.

4. The apparatus of claim 3 wherein the read channel circuitry further comprises an averaging module and the retry mode of operation utilizes an X-averaging operation performed by the averaging module.

5. The apparatus of claim 3 wherein the X samples further comprise X samples from multiple distinct digital read signal streams.

6. The apparatus of claim 5 wherein the X samples further comprise averaged X samples generated using the X samples from the multiple distinct digital read signal streams.

7. The apparatus of claim 1 wherein the subsector bridging control module is configured to cause the despreader to insert a sufficient number of bridging bits between each pair of adjacent subsectors of the stitched logic sector so as to prevent stitching boundary discontinuities that might otherwise arise from use of X-averaging in generation of Y samples from X samples in a retry mode of operation.

8. The apparatus of claim 1 wherein the number of bridging bits to be inserted between the given pair of adjacent subsectors of the stitched logic sector is determined automatically by the subsector bridging control module as a function of a number of taps included in a DFIR filter to be applied to the stitched logic sector in a retry mode of operation.

9. The apparatus of claim 8 wherein the DFIR filter comprises a 16-tap DFIR filter and the subsector bridging control module causes the despreader to insert 16 warm-up bits preceding each subsector, 16 cool-down bits following each subsector other than a final subsector, and 20 padding bits following the final subsector.

10. The apparatus of claim 8 wherein the DFIR filter comprises a 12-tap DFIR filter and the subsector bridging control module causes the despreader to insert 12 warm-up bits preceding each subsector, 12 cool-down bits following each subsector other than a final subsector, and 20 padding bits following the final subsector.

11. The apparatus of claim 1 wherein the subsector bridging control module is further configured to control a number of bridging bits inserted by the despreader between a given pair of adjacent portions of a split subsector of the stitched logic sector.

12. The apparatus of claim 1 wherein the subsector bridging control module is at least partially incorporated within the despreader.

13. The apparatus of claim 1 wherein the read channel circuitry is fabricated in at least one integrated circuit.

14. A method comprising the steps of:

receiving a read data signal;

generating a stitched logic sector from the read data signal by stitching together subsectors of that logic sector that were interleaved with subsectors of other logic sectors for storage on a storage medium; and

controlling a number of bridging bits inserted between a given pair of adjacent subsectors of the stitched logic sector.

15. The method of claim 14 wherein the stitched logic sector comprises X samples that are provided to a DFIR filter for use in generating Y samples in a retry mode of operation.

16. The method of claim 14 wherein controlling the number of bridging bits comprises controlling insertion of a sufficient number of bridging bits between each pair of adjacent subsectors of the stitched logic sector so as to prevent stitching boundary discontinuities that might otherwise arise from use of X-averaging in generation of Y samples from X samples in a retry mode of operation.

17. The method of claim 14 wherein controlling the number of bridging bits comprises automatically determining the number of bridging bits to be inserted between the given pair of adjacent subsectors of the stitched logic sector as a function of a number of taps included in a DFIR filter to be applied to the stitched logic sector in a retry mode of operation.

18. An article of manufacture comprising a computer-readable storage medium having computer program code embodied therein, wherein the computer program code when executed causes the storage device to perform the method of claim 14 .

19. A storage device comprising:

a storage medium;

a read/write head; and

read channel circuitry coupled to the read/write head;

the read channel circuitry comprising:

a despreader configured to generate a stitched logic sector by stitching together subsectors of that logic sector that were interleaved with subsectors of other logic sectors for storage on the storage medium; and

a subsector bridging control module associated with the despreader and configured to control a number of bridging bits inserted by the despreader between a given pair of adjacent subsectors of the stitched logic sector.

20. A virtual storage system comprising the storage device of claim 19 .

Assignments (10)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2014
From: LU, LU; XIA, HAITAO; JEONG, KU HONG; YANG, YUQING
To: LSI CORPORATION
Reel/Frame 032654/0766 →