WORD LINE DECODERS FOR DUAL RAIL STATIC RANDOM ACCESS MEMORIES
Word line decoders for dual rail SRAM devices are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a word line traversing the memory cell array for selecting memory cells of the memory cell array. A row decode-driver coupled to the word line toggles the word line between logic levels of a memory cell supply based on select signals that toggle between logic levels of a peripheral supply. The row decoder-driver toggles the word line without utilizing level shifters along the word line access path.
1 . A Static Random Access Memory (SRAM) device, comprising:
a memory cell array;
a word line traversing the memory cell array for selecting memory cells of the memory cell array;
a level shift circuit configured receive a first select signal that toggles between logic levels defined by a peripheral supply, and to translate the first select signal to logic levels defined by a memory cell supply to generate a level-shifted select signal; and
a row decode-driver configured to toggle the word line, the row decode-driver comprising:
an inverting driver coupled to the word line and configured to toggle the word line between the logic levels defined by the memory cell supply based on an internal signal;
a first pull-up circuit configured to couple the internal signal to the memory cell supply based on the level-shifted select signal and the first select signal;
a second pull-up circuit configured to couple the internal signal to the memory cell supply based on a logic level of the word line and a second select signal, wherein the second select signal toggles between the logic levels defined by the peripheral supply; and
a pull-down circuit configured to couple the internal signal to ground based on the first select signal and the second select signal.
2 . The SRAM device of claim 1 wherein the first pull-up circuit comprises:
a first P-channel Field Effect Transistor (FET) having a source terminal coupled to the memory cell supply, a gate terminal coupled to the level-shifted select signal, and a drain terminal; and
a second P-channel FET having a source terminal coupled to the drain terminal of the first FET, a gate terminal coupled to the first select signal, and a drain terminal coupled to the internal signal.
3 . The SRAM device of claim 1 wherein the second pull-up circuit comprises:
a first P-channel Field Effect Transistor (FET) having a source terminal coupled to the memory cell supply, a gate terminal coupled to the word line, and a drain terminal; and
a second P-channel FET having a source terminal coupled to the drain terminal of the first FET, a gate terminal coupled to the second select signal, and a drain terminal coupled to the internal signal.
4 . The SRAM device of claim 1 wherein the pull-down circuit comprises:
a first N-channel Field Effect Transistor (FET) having a drain terminal coupled to the internal signal, a gate terminal coupled to the second select signal, and a source terminal; and
a second N-channel FET having a drain terminal coupled to the source terminal of the first FET, a gate terminal coupled to the first select signal, and a drain terminal coupled to ground.
5 . The SRAM device of claim 1 wherein the inverting driver comprises:
a first P-channel Field Effect Transistor (FET) having a source terminal coupled to the memory cell supply, a gate terminal coupled to the internal signal, and a drain terminal coupled to the word line; and
a second N-channel FET having a drain terminal coupled to the word line, a gate terminal coupled to the internal signal, and a source terminal coupled to the ground.
6 . The SRAM device of claim 1 wherein the ground is a common ground for the peripheral supply and the memory cell supply.
7 . The SRAM device of claim 1 wherein the first select signal and the second select signal toggle to a logical one to set the word line to a logical one.
8 . The SRAM device of claim 1 wherein the first select signal toggles to a logical zero to set the word line to a logical zero.
9 . A Static Random Access Memory (SRAM) device, comprising:
a memory cell array;
a word line traversing the memory cell array for selecting memory cells of the memory cell array; and
a row decode-driver configured to toggle the word line, the row decode-driver comprising:
an inverting driver coupled to the word line and configured to toggle the word line between logic levels defined by a memory cell supply based on an internal signal;
a first P-channel Field Effect Transistor (FET) having a source terminal, a gate terminal coupled to a first select signal, and a drain terminal coupled to the internal signal, wherein the first select signal toggles between logic levels defined by a peripheral supply;
a second P-channel FET having a source terminal coupled to the memory cell supply, a drain terminal coupled to the source terminal of the first FET, and a gate terminal coupled to a level-shifted signal generated by translating the first select signal to the logic levels defined by the memory cell supply;
a third P-channel FET having a source terminal coupled to the memory cell supply, a gate terminal coupled to the word line, and a drain terminal;
a fourth P-channel FET having a source terminal coupled to the drain terminal of the third FET, a drain terminal coupled to the internal signal, and a gate terminal coupled to a second select signal, wherein the second select signal toggles between the logic levels defined by the peripheral supply;
a fifth N-channel FET having a drain terminal coupled to the internal signal, a gate terminal coupled to the second select signal, and a source terminal; and
a sixth N-channel FET having a drain terminal coupled to the source terminal of the fifth FET, a gate terminal coupled to the first select signal, and a drain terminal coupled to ground.
10 . The SRAM device of claim 9 wherein the ground is a common ground for the peripheral supply and the memory cell supply.
11 . The SRAM device of claim 9 wherein the first select signal and the second select signal toggle to a logical one to set the word line to a logical one.
12 . The SRAM device of claim 9 wherein the first select signal toggles to a logical zero to set the word line to a logical zero.
13 . The SRAM device of claim 9 wherein the inverting driver comprises:
a seventh P-channel FET having a source terminal coupled to the memory cell supply, a gate terminal coupled to the internal signal, and a drain terminal coupled to the word line; and
an eighth N-channel FET having a drain terminal coupled to the word line, a gate terminal coupled to the internal signal, and a source terminal coupled to the ground.
14 . The SRAM device of claim 9 further comprising:
a level shift circuit configured to translate the first select signal from the logic levels of the peripheral supply to the logic levels of the memory cell supply.
15 . A Static Random Access Memory (SRAM) device, comprising:
a memory cell array;
a word line traversing the memory cell array for selecting memory cells of the memory cell array, wherein the word line toggles between logic levels defined by a memory cell supply for the memory cells;
a plurality of decode lines for selecting the word line, wherein the plurality of decode lines toggle between logic levels defined by a peripheral supply;
a level shift circuit configured to receive a first decode signal received from one of the plurality of decode lines, and to translate the first decode signal to logic levels defined by the memory cell supply to generate a level-shifted decode signal; and
a row decode-driver configured to toggle the word line, the row decode-driver comprising:
an inverting driver having an output coupled to the word line and an input; and
a decode circuit coupled to the input of the inverting driver and configured to couple the input of the inverting driver to the memory cell supply based on the level-shifted decode signal, the first decode signal, a logic level of the word line, and a second decode signal;
the decode circuit further configured to couple the input of the inverting driver to ground based on the first decode signal and the second decode signal.
16 . The SRAM device of claim 15 wherein a voltage of the peripheral supply is less than a voltage of the memory cell supply.
17 . The SRAM device of claim 15 wherein the ground is a common ground for the peripheral supply and the memory cell supply.
18 . The SRAM device of claim 15 wherein the first decode signal and the second decode signal toggle to a logical one to set the word line to a logical one.
19 . The SRAM device of claim 15 wherein the first decode signal toggles to a logical zero to set the word line to a logical zero.
20 . The SRAM device of claim 15 wherein the decoder comprises:
a first P-channel Field Effect Transistor (FET) having a source terminal coupled to the memory cell supply, a gate terminal coupled to the level-shifted decode signal, and a drain terminal;
a second P-channel FET having a source terminal coupled to the drain terminal of the first FET, a gate terminal coupled to the first decode signal, and a drain terminal coupled to the input of the inverting driver;
a third P-channel FET having a source terminal coupled to the memory cell supply, a gate terminal coupled to the word line, and a drain terminal;
a fourth P-channel FET having a source terminal coupled to the drain terminal of the third FET, a gate terminal coupled to the second decode signal, and a drain terminal coupled to the input of the inverting driver;
a fifth N-channel FET having a drain terminal coupled to the input of the inverting driver, a gate terminal coupled to the second decode signal, and a source terminal; and
a sixth N-channel FET having a drain terminal coupled to the source terminal of the fifth FET, a gate terminal coupled to the first decode signal, and a drain terminal coupled to the ground.