IP Library Granted Patent US 9,172,355
Granted Patent B2
US 9,172,355 · App. 14/264,954 · Granted Oct 27, 2015

Transmission circuit and signal transmission and reception circuit

Inventors: Hiroyuki Sato (Kawasaki, JP); Yoshihiko Matsuo (Kawasaki, JP)
Assignees: FUJITSU LIMITED; FUJITSU SEMICONDUCTOR LIMITED
H03H11/348H03H7/38H03H7/42
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Quick Facts
Patent No.
US 9,172,355
App. No.
14/264,954
Granted
Oct 27, 2015
Kind
B2
Abstract

A transmission circuit includes a first path that connects a first terminal for inputting or outputting signals, and one of a pair of second terminals for outputting or inputting the signals; a second path that connects the first terminal and another one of the pair of second terminals; a first circuit including a first capacitor that is serially inserted in the first path, which is configured to perform single-differential conversion on signals transmitted through the first path, to perform impedance matching, and to supply a bias voltage; a second circuit including a first inductor that is serially inserted in the second path, which is configured to perform single-differential conversion on signals transmitted through the second path, to perform impedance matching, and to supply a bias voltage; and a switch that is connected between the two terminals of the pair of second terminals.

Claims (81)

1. A transmission circuit comprising:

a first terminal for inputting or outputting signals;

a pair of second terminals for outputting or inputting the signals;

a first path that connects the first terminal and one of the pair of second terminals;

a second path that connects the first terminal and another one of the pair of second terminals;

a first circuit including a first capacitor that is serially inserted in the first path, the first capacitor being inserted between the first terminal and the one of the pair of second terminals, the first circuit being configured to perform single-differential conversion on signals transmitted through the first path, to perform impedance matching, and to supply a bias voltage;

a second circuit including a first inductor that is serially inserted in the second path, the first inductor being inserted between the first terminal and the other one of the pair of second terminals, the second circuit being configured to perform single-differential conversion on signals transmitted through the second path, to perform impedance matching, and to supply a bias voltage; and

a switch that is connected between the one of the pair of second terminals and the other one of the pair of second terminals,

wherein

the first circuit includes:

the first capacitor,

a first branch path that branches from between the first capacitor and the one of the pair of second terminals, and that is connected to a reference potential point,

a first parallel circuit that is serially inserted in the first branch path, the first parallel circuit including a second inductor and a second capacitor, and

a first DC power source that is serially inserted in the first branch path, between the first parallel circuit and the reference potential point, and wherein

the second circuit includes:

the first inductor,

a second branch path that branches from between the first inductor and the other one of the pair of second terminals, and that is connected to the reference potential point,

a second parallel circuit that is serially inserted in the second branch path, the second parallel circuit including a third inductor and a third capacitor, and

a second DC power source that is serially inserted in the second branch path, between the second parallel circuit and the reference potential point.

2. The transmission circuit according to claim 1 , wherein

a resonance frequency that is determined according to a capacitance of the first capacitor and an inductance of the first inductor is equal to a resonance frequency of the signals transmitted through the first path and the second path.

3. The transmission circuit according to claim 1 , further comprising:

a fourth capacitor that is inserted between the first terminal, and the first capacitor and the first inductor.

4. A transmission circuit comprising:

a first terminal for inputting or outputting signals;

a pair of second terminals for outputting or inputting the signals;

a first path that connects the first terminal and one of the pair of second terminals;

a second path that connects the first terminal and another one of the pair of second terminals;

a first circuit including a first capacitor that is serially inserted in the first path, the first capacitor being inserted between the first terminal and the one of the pair of second terminals, the first circuit being configured to perform single-differential conversion on signals transmitted through the first path, and to perform impedance matching;

a second circuit including a first inductor that is serially inserted in the second path, the first inductor being inserted between the first terminal and the other one of the pair of second terminals, the second circuit being configured to perform single-differential conversion on signals transmitted through the second path, and to perform impedance matching; and

a switch that is connected between the one of the pair of second terminals and the other one of the pair of second terminals,

wherein

the first circuit includes:

the first capacitor,

a first branch path that branches from between the first capacitor and the one of the pair of second terminals, and that is connected to a reference potential point, and

a first parallel circuit that is serially inserted in the first branch path, the first parallel circuit including a second inductor and a second capacitor, and wherein

the second circuit includes:

the first inductor,

a second branch path that branches from between the first inductor and the other one of the pair of second terminals, and that is connected to the reference potential point, and

a second parallel circuit that is serially inserted in the second branch path, the second parallel circuit including a third inductor and a third capacitor.

5. A signal transmission and reception circuit comprising:

a signal transmission and reception terminal;

a transmitting circuit configured to include a pair of output terminals and to transmit signals; and

the transmission circuit according to claim 1 , wherein the transmission circuit is provided between the signal transmission and reception terminal and the transmitting circuit, and wherein the first terminal is connected to the signal transmission and reception terminal, and the pair of second terminals are connected to the pair of output terminals of the transmitting circuit.

6. The signal transmission and reception circuit according to claim 5 , wherein

the switch and the transmitting circuit are realized as a single semiconductor circuit device.

7. A signal transmission and reception circuit comprising:

a signal transmission and reception terminal;

a receiving circuit configured to include a pair of input terminals and to receive signals; and

the transmission circuit according to claim 1 , wherein the transmission circuit is provided between the signal transmission and reception terminal and the receiving circuit, and wherein the first terminal is connected to the signal transmission and reception terminal, and the pair of second terminals are connected to the pair of input terminals of the receiving circuit.

8. The signal transmission and reception circuit according to claim 7 , wherein

the switch and the receiving circuit are realized as a single semiconductor circuit device.

9. A transmission circuit comprising:

a first path that connects a first terminal for inputting or outputting signals, and one of a pair of second terminals for outputting or inputting the signals;

a second path that connects the first terminal and another one of the pair of second terminals;

a first capacitor that is serially inserted in the first path;

a first inductor that is serially inserted in the second path;

a first branch path that branches from between the first capacitor of the first path and the one of the pair of second terminals, and that is connected to a reference potential point;

a first parallel circuit that is serially inserted in the first branch path, the first parallel circuit including a second inductor and a second capacitor;

a first DC power source that is serially inserted in the first branch path, between the first parallel circuit and the reference potential point;

a second branch path that branches from between the first inductor of the second path and the other one of the pair of second terminals, and that is connected to the reference potential point;

a second parallel circuit that is serially inserted in the second branch path, the second parallel circuit including a third inductor and a third capacitor;

a second DC power source that is serially inserted in the second branch path, between the second parallel circuit and the reference potential point; and

a switch that is connected between the one of the pair of second terminals and the other one of the pair of second terminals.

10. The transmission circuit according to claim 9 , wherein

a resonance frequency that is determined according to a capacitance of the first capacitor and an inductance of the first inductor is equal to a resonance frequency of the signals transmitted through the first path and the second path.

11. A signal transmission and reception circuit comprising:

a signal transmission and reception terminal;

a transmitting circuit configured to include a pair of output terminals and to transmit signals; and

the transmission circuit according to claim 9 , wherein the transmission circuit is provided between the signal transmission and reception terminal and the transmitting circuit, and wherein the first terminal is connected to the signal transmission and reception terminal, and the pair of second terminals are connected to the pair of output terminals of the transmitting circuit.

12. The signal transmission and reception circuit according to claim 11 , wherein

the switch and the transmitting circuit are realized as a single semiconductor circuit device.

13. A signal transmission and reception circuit comprising:

a signal transmission and reception terminal;

a receiving circuit configured to include a pair of input terminals and to receive signals; and

the transmission circuit according to claim 10 , wherein the transmission circuit is provided between the signal transmission and reception terminal and the receiving circuit, and wherein the first terminal is connected to the signal transmission and reception terminal, and the pair of second terminals are connected to the pair of input terminals of the receiving circuit.

14. The signal transmission and reception circuit according to claim 13 , wherein

the switch and the receiving circuit are realized as a single semiconductor circuit device.

15. The signal transmission and reception circuit according to claim 9 , further comprising:

a first circuit including the first capacitor that is serially inserted in the first path, the first capacitor being inserted between the first terminal and the one of the pair of second terminals, the first circuit being configured to perform single-differential conversion on signals transmitted through the first path, to perform impedance matching, and to supply a bias voltage; and

a second circuit including the first inductor that is serially inserted in the second path, the first inductor being inserted between the first terminal and the other one of the pair of second terminals, the second circuit being configured to perform single-differential conversion on signals transmitted through the second path, to perform impedance matching, and to supply a bias voltage.

Assignments (5)
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2019
From: FUJITSU LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 050643/0022 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2014
From: SATO, HIROYUKI; MATSUO, YOSHIHIKO
To: FUJITSU LIMITED; FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 033779/0824 →
Priority Claims (1)
JP 2013-097008 · May 2, 2013 · national
Continuity (1)
Related Publication 20140327494A1 · Nov 6, 2014