IP Library Granted Patent US 9,304,876
Granted Patent B2
US 9,304,876 · App. 14/269,410 · Granted Apr 5, 2016

Logical volume migration in single server high availability environments

Inventors: Naresh Madhusudana (Bangalore, IN); Naveen Krishnamurthy (Bangalore, IN); Sridhar Rao Veerla (Bangalore, IN)
Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
G06F11/2017G06F11/2082G06F11/3027G06F13/4221G06F2201/84
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Quick Facts
Patent No.
US 9,304,876
App. No.
14/269,410
Granted
Apr 5, 2016
Kind
B2
Abstract

Methods and structure for migrating logical volumes are provided. The system includes a Redundant Array of Independent Disks controller, which includes a Peripheral Component Interconnect Express interface, a Serial Attached Small Computer System Interface port operable to communicate with another Redundant Array of Independent Disks controller, and a command unit. The command unit is able to direct the interface to access another Peripheral Component Interconnect Express interface at the other controller, to synchronize with Disk Data Format information from a Peripheral Component Interconnect Express Inbound Map of the other interface, to detect that the other controller has failed, and to utilize the Disk Data Format information to migrate a logical volume from the other controller to the controller.

Claims (53)

1. A system comprising:

a Redundant Array of Independent Disks controller comprising:

a Peripheral Component Interconnect Express interface;

a Serial Attached Small Computer System Interface port operable to communicate with another Redundant Array of Independent Disks controller; and

a command unit operable to direct the interface to access another Peripheral Component Interconnect Express interface at the other controller, to synchronize with Disk Data Format information from a Peripheral Component Interconnect Express Inbound Map of the other interface, to detect that the other controller has failed, and to utilize the Disk Data Format information to migrate a logical volume from the other controller to the controller.

2. The system of claim 1 , wherein:

the interface comprises a Peripheral Component Interconnect Express Inbound Map that includes Disk Data Format information describing a logical volume owned by the controller.

3. The system of claim 1 , wherein:

the interface comprises a Peripheral Component Interconnect Express Inbound Map that includes Serial Attached Small Computer System Interface discovery information acquired by the controller.

4. The system of claim 1 , wherein:

the command unit is further operable to identify status information for the other controller stored in the Peripheral Component Interconnect Express Inbound Map of the other interface, and to migrate the logical volume if the status information indicates a failure of the other controller.

5. The system of claim 1 , wherein:

the command unit is further operable to detect a change in Serial Attached Small Computer System Interface topology, to detect Serial Attached Small Computer System Interface discovery information stored in the Peripheral Component Interconnect Express Inbound Map of the other interface, and to utilize the discovery information to accelerate discovery at the controller.

6. The system of claim 5 , wherein:

the command unit is further operable to identify multiple Serial Attached Small Computer System Interface devices based on the discovery information, and to confirm the existence of the devices by sending a Test Unit Ready command to each of the devices.

7. The system of claim 1 , wherein:

the command unit is further operable to store a Base Address Register indicating an address of the other controller.

8. A method comprising:

operating a Peripheral Component Interconnect Express interface of a Redundant Array of Independent Disks controller to access another Peripheral Component Interconnect Express interface at another Redundant Array of Independent Disks controller, wherein the controller is operable to communicate with the other controller via a Serial Attached Small Computer System Interface port;

directing the interface to synchronize with Disk Data Format information from a Peripheral Component Interconnect Express Inbound Map of the other interface;

detecting that the other controller has failed; and

utilizing the Disk Data Format information to migrate a logical volume from the other controller to the controller.

9. The method of claim 8 , wherein:

the interface comprises a Peripheral Component Interconnect Express Inbound Map that includes Disk Data Format information describing a logical volume owned by the controller.

10. The method of claim 8 , wherein:

the interface comprises a Peripheral Component Interconnect Express Inbound Map that includes Serial Attached Small Computer System Interface discovery information acquired by the controller.

11. The method of claim 8 , further comprising:

identifying status information for the other controller stored in the Peripheral Component Interconnect Express Inbound Map of the other interface; and

migrating the logical volume if the status information indicates a failure of the other controller.

12. The method of claim 8 , further comprising:

detecting a change in Serial Attached Small Computer System Interface topology;

detecting Serial Attached Small Computer System Interface discovery information stored in the Peripheral Component Interconnect Express Inbound Map of the other interface; and

utilizing the discovery information to accelerate discovery at the controller.

13. The method of claim 12 , further comprising:

identifying multiple Serial Attached Small Computer System Interface devices based on the discovery information; and

confirming the existence of the devices by sending a Test Unit Ready command to each of the devices.

14. The method of claim 8 , further comprising:

storing a Base Address Register at the controller indicating an address of the other controller.

15. A system comprising:

a Redundant Array of Independent Disks controller comprising:

a Peripheral Component Interconnect Express interface;

a Serial Attached Small Computer System Interface port operable to communicate with another Redundant Array of Independent Disks controller; and

a means for directing the interface to access another Peripheral Component Interconnect Express interface at the other controller, synchronizing with Disk Data Format information from a Peripheral Component Interconnect Express Inbound Map of the other interface, detecting that the other controller has failed, and utilizing the Disk Data Format information to migrate a logical volume from the other controller to the controller.

16. The system of claim 15 , wherein:

the interface comprises a Peripheral Component Interconnect Express Inbound Map that includes Disk Data Format information describing a logical volume owned by the controller.

17. The system of claim 15 , wherein:

the interface comprises a Peripheral Component Interconnect Express Inbound Map that includes Serial Attached Small Computer System Interface discovery information acquired by the controller.

18. The system of claim 15 , wherein:

the means are further for identifying status information for the other controller stored in the Peripheral Component Interconnect Express Inbound Map of the other interface, and migrating the logical volume if the status information indicates a failure of the other controller.

19. The system of claim 15 , wherein:

the means are further for detecting a change in Serial Attached Small Computer System Interface topology, detecting Serial Attached Small Computer System Interface discovery information stored in the Peripheral Component Interconnect Express Inbound Map of the other interface, and utilizing the discovery information to accelerate discovery at the controller.

20. The system of claim 19 , wherein:

the means are further for identifying multiple Serial Attached Small Computer System Interface devices based on the discovery information, and confirming the existence of the devices by sending a Test Unit Ready command to each of the devices.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2014
From: MADHUSUDANA, NARESH; KRISHNAMURTHY, NAVEEN; VEERLA, SRIDHAR RAO
To: LSI CORPORATION
Reel/Frame 032820/0337 →
Continuity (1)
Related Publication 20150317219A1 · Nov 5, 2015