Semi conductor device having elevated source and drain
Semiconductor layers on active areas for transistors in a memory cell region (region A) and a peripheral circuit region (region B) are simultaneously epitaxially grown in the same thickness in which the adjacent semiconductor layers in region A do not come into contact with each other. Only semiconductor layer ( 10 ) in region B is also grown from the surface of a substrate which is exposed when only the surface of STI ( 2 ) in region B is drawn back, so that a facet (F) of the semiconductor layer 10 is formed outside the active area, followed by ion-implantation to form a high density diffusion layer ( 11 ) in region B. Accordingly, short circuit between semiconductor layers on source/drain electrodes of transistors in region A is prevented, and uniformity of the junction depth of the layer ( 11 ) of the source/drain electrodes including an ESD region in a transistor of region B is obtained, thereby restricting the short channel effect.
1. A semiconductor device comprising:
a memory cell region having a memory device and a cell transistor electrically connected to the memory device, and
a peripheral circuit region in which a peripheral circuit transistor is formed;
wherein the cell transistor comprises, in a first active area of a semiconductor substrate zoned by a shadow trench isolation:
a first gate electrode;
first source/drain regions formed on both sides of the first gate electrode; and
a first selectively epitaxially grown semiconductor layer formed on the first source/drain regions,
wherein the peripheral circuit transistor comprises, in a second active area of the semiconductor substrate zoned by a shallow trench isolation:
a second gate electrode;
second source/drain regions of an LDD structure including a high density impurity diffusion layer formed on both sides of the second gate electrode; and
elevated source/drain regions formed from a second selectively epitaxially grown semiconductor layer formed on the second source/drain regions;
wherein the first and second selectively epitaxially grown semiconductor layers of the cell transistor and the peripheral circuit transistor, respectively, have a substantially similar thickness such that the semiconductor layers provided on first active areas of adjacent cell transistors opposite to each other do not contact each other;
wherein a surface of the shallow trench isolation in the peripheral circuit, region is drawn back From a surface of the semiconductor substrate, and
wherein a surface of the shallow trench isolation in the memory cell region is not drawn back from a surface of the semiconductor substrate.
2. A semiconductor device comprising;
a cell transistor provided in a memory cell region,
a peripheral circuit transistor provided in a peripheral circuit region, and
a shallow trench isolation defining each active area of the cell transistor and the peripheral circuit transistor in a semiconductor substrate;
wherein the cell transistor comprises a first impurity diffusion layer, a first gate electrode and a first gate sidewall spacer;
wherein the peripheral circuit transistor comprises a first impurity diffusion layer, a second impurity diffusion layer, a second gate electrode and a second gate sidewall spacer;
wherein the second impurity diffusion layer is higher in impurity density than the first impurity diffusion layer of the peripheral circuit transistor;
wherein a selectively epitaxially grown semiconductor layer is provided on the first impurity diffusion layer of the cell transistor and the second impurity diffusion layer of the peripheral circuit transistor;
wherein the shallow trench isolation defining the active area of the cell transistor is not drawn back from a surface of the semiconductor substrate so that a first side surface of the semiconductor substrate is not exposed;
wherein the shallow trench isolation defining the active area of the peripheral circuit transistor is drawn back from a surface of the semiconductor substrate so that a second side surface of the semiconductor substrate is exposed; and
wherein the cell transistor further comprises a first contact plug electrically connected between the selectively epitaxially grown semiconductor layer and a bit line.