IP Library Granted Patent US 9,749,173
Granted Patent B2
US 9,749,173 · App. 14/275,920 · Granted Aug 29, 2017

Systems and methods for synchronizing forwarding databases across multiple interconnected layer-2 switches

Inventors: Vineet Gautam (Dwarka, IN); Prashant Vashisht (Gurgaon, IN); Anup Kumar (Noida, IN); Mukesh Chhabra (New Delhi, IN)
Assignee: Ciena Corporation
H04L29/0653H04L45/245H04L49/15H04L41/0213H04L47/125Y02B60/33
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Quick Facts
Patent No.
US 9,749,173
App. No.
14/275,920
Granted
Aug 29, 2017
Kind
B2
Abstract

A method and a multi-switch architecture include learning a media access control (MAC) address at a first switch in a multi-switch architecture; storing the MAC address in a forwarding database of the first switch; transmitting a data frame to one or more switches in the multi-switch architecture via inter-switch connectivity between the first switch and the one or more switches, wherein the data frame is created to enable the one or more switches to learn the MAC address therefrom; learning the MAC address from the data frame at the one or more switches; and storing the MAC address in a forwarding database for each of the one or more switches. This further includes transmitting the data frame via ports and queues in the inter-switch connectivity that are separate from ports and queues in a data path between the first switch and the one or more switches to avoid data path interference.

Claims (45)

1. A method implemented by a plurality of interconnected switches in a multi-switch architecture, the method comprising:

learning a media access control (MAC) address at a first switch in a multi-switch architecture;

storing the MAC address in a forwarding database of the first switch;

transmitting a synch data frame to one or more switches in the multi-switch architecture via inter-switch connectivity between the first switch and the one or more switches for synchronization using a distributed approach, wherein the inter-switch connectivity comprises at least two ports and queues comprising a data path queue and a separate queue between each of the plurality of interconnected switches, wherein each of the data path queue and the separate queue are configured for transmitting data frames between each of the plurality of interconnected switches, wherein the synch data frame is created to enable the one or more switches to learn the MAC address therefrom, wherein the transmitting of the sync data frame is via the separate queue that is separate from the data path queue, wherein the separate queue is constrained to only provide synch data frames between the plurality of interconnected switches, and wherein the distributed approach assigns slots to transmit learned MAC addresses over time based on a time offset determined based on the learned MAC address for the transmitting;

learning the MAC address from the data frame at the one or more switches; and

storing the MAC address in a forwarding database for each of the one or more switches.

2. The method of claim 1 , further comprising:

transmitting the data frame with a source address comprising the MAC address and a switch destination set such that all switches in the multi-switch architecture receive the data frame.

3. The method of claim 1 , wherein the data frame comprises a first data frame, and further comprising:

transmitting the first data frame to the one or more switches in one direction; and

transmitting a second data frame in another direction on the inter-switch connectivity to another switch in the multi-switch architecture, wherein the second data frame is created to enable the another switch to learn the MAC address therefrom.

4. The method of claim 1 , further comprising:

transmitting the data frame with a source address comprising the MAC address, a switch destination set such that all switches in the multi-switch architecture receive the data frame, and an invalid destination port so the data frame is dropped at the switch destination.

5. The method of claim 1 , further comprising:

transmitting the data frame as a sync unicast packet comprising an inter-switch header and a Layer-2 header.

6. The method of claim 5 , wherein the inter-switch header comprises a source switch indicator identifying the first switch, a source port identifier identifying a port on the first switch which learned the MAC address, a destination switch comprising a last switch of the one or more switches, and a destination port set to an invalid port on the last switch; and

wherein the Layer-2 header comprises any value for a destination address, a source address set to the MAC address, and empty data.

7. The method of claim 1 , wherein the first switch and the one or more switches are configured in a link aggregation group.

8. The method of claim 1 , wherein the inter-switch connectivity operates on a backplane of a chassis.

9. The method of claim 1 , further comprising:

upon learning the MAC address at the first switch and transmitting the data frame, establishing a synchronization refresh timer less than an aging time for the MAC address; and

resending the data frame at an expiration of the synchronization refresh timer.

10. The method of claim 1 , wherein the first switch and the one or more switches are managed as a single switch from a network element perspective and a network management perspective.

11. A multi-switch architecture, comprising:

a plurality of interconnected switches each comprising one or more ports thereon and a forwarding database;

inter-switch connectivity connecting the plurality of interconnected switches, wherein the inter-switch connectivity comprises at least two ports and queues between each of the plurality of interconnected switches;

data path queues associated with the inter-switch connectivity; and

a dedicated queue associated with the inter-switch connectivity and separate from the data path queues, wherein both the data path queues and the dedicated queue are each configured for transmission of data frames between each of the plurality of interconnected switches, wherein the dedicated queue is only configured for the exchange of synch data frames between the plurality of interconnected switches for synchronization of the forwarding database of each of the plurality of interconnect switches using a distributed approach;

wherein, upon learning a new media access control (MAC) address on a port of the one or more ports of a switch of the plurality of interconnected switches, the switch transmits a sync data frame on through the dedicated queue for the remaining interconnected switches to learn the new MAC address, and wherein the distributed approach assigns slots to transmit learned new MAC addresses over time based on a time offset determined based on the learned new MAC address.

12. The multi-switch architecture of claim 11 , wherein the data frame comprises a source address comprising the new MAC address and a switch destination set such that all switches in the multi-switch architecture receive the data frame.

13. The multi-switch architecture of claim 11 , wherein the data frame comprises a source address comprising the new MAC address, a switch destination set such that all switches in the multi-switch architecture receive the data frame, and an invalid destination port so the data frame is dropped at the switch destination.

14. The multi-switch architecture of claim 11 , wherein the data frame comprises a sync unicast packet comprising an inter-switch header and a Layer-2 header.

15. The multi-switch architecture of claim 14 , wherein the inter-switch header comprises a source switch indicator identifying the switch, a source port identifier identifying a port on the switch which learned the MAC address, a destination switch comprising a last switch of the plurality of interconnected switches, and a destination port set to an invalid port on the last switch; and

wherein the Layer-2 header comprises any value for a destination address, a source address set to the MAC address, and empty data.

16. The multi-switch architecture of claim 11 , wherein the plurality of switches are configured in a link aggregation group.

17. The multi-switch architecture of claim 11 , wherein the inter-switch connectivity operates on a backplane of a chassis.

18. The multi-switch architecture of claim 11 , wherein the plurality of interconnected switches are managed as a single switch from a network element perspective and a network management perspective.

19. A switch, comprising:

a plurality of ports;

switching circuitry communicatively coupled to the plurality of ports;

a forwarding database communicatively coupled to the switching circuitry; and

inter-switch connectivity connecting the switch to one or more switches collectively forming a multi-switch architecture managed as a single network element, wherein the inter-switch connectivity comprises at least two ports and queues comprising a data path queue and a separate queue between each of the plurality of interconnected switches between the switch and the one or more switches, and wherein each of the data path queue and the separate queue is configured for transmission of data frames between each of the plurality of interconnected switches;

wherein the switch is configured to:

learn new media access control (MAC) addresses received on data ports and ports dedicated to receiving sync packets on the inter-switch connectivity; and

transmit a sync packet on ports dedicated to only transmitting sync packets on the inter-switch connectivity using a distributed approach, wherein the sync packets comprise a source address set to a MAC address to be learned, a destination switch set to a last switch in the one or more switches, and a destination port set to invalid, wherein the sync packet is transmitted through only the separate queue, and wherein the distributed approach assigns slots to transmit learned MAC addresses over time based on a time offset determined based on the learned MAC address for transmission of the sync packet.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2023
From: BANK OF AMERICA, N.A.
To: CIENA CORPORATION
Reel/Frame 065630/0232 →
PATENT SECURITY AGREEMENT Recorded Nov 8, 2019
From: CIENA CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 050969/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 30, 2019
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: CIENA CORPORATION
Reel/Frame 050938/0389 →
PATENT SECURITY AGREEMENT Recorded Jul 16, 2014
From: CIENA CORPORATION
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 033347/0260 →
SECURITY INTEREST Recorded Jul 15, 2014
From: CIENA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 033329/0417 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2014
From: GAUTAM, VINEET; VASHISHT, PRASHANT; KUMAR, ANUP; CHHABRA, MUKESH
To: CIENA CORPORATION
Reel/Frame 032884/0541 →
Priority Claims (2)
IN 2838/DEL/2012 · Sep 11, 2012 · national
IN 924/DEL/2014 · Mar 31, 2014 · national
Continuity (2)
Continuation In Part 13659554 · Oct 24, 2012
Related Publication 20140247829A1 · Sep 4, 2014