IP Library Granted Patent US 9,384,138
Granted Patent B2
US 9,384,138 · App. 14/276,429 · Granted Jul 5, 2016

Temporal tracking of cache data

Inventors: Vinay Bangalore Shivashankaraiah (Bangalore, IN); Kumaravel Thillai (Tamilnadu, IN)
Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
G06F12/0871G06F12/0802G06F12/122G06F2212/26G06F2212/28G06F2212/604G06F2212/69
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Quick Facts
Patent No.
US 9,384,138
App. No.
14/276,429
Granted
Jul 5, 2016
Kind
B2
Abstract

A data storage system with a cache organizes cache windows into lists based on the number of cache lines accessed during input/output operations. The lists are maintained in temporal queues with cache windows transferred from prior temporal queues to a current temporal queue. Cache windows are removed from the oldest temporal queue and least accessed cache window list whenever cached data needs to be removed for new hot data.

Claims (50)

1. A computer apparatus, comprising:

a processor;

memory connected to the processor, at least a portion of the memory comprising a cache; and

computer executable program code configured to execute on the processor,

wherein the computer executable program code is configured to:

receive an input/output operation;

identify a cache window associated with data to be accessed pursuant to the input/output operation;

remove the cache window from a prior temporal queue; and

add the cache window to a current temporal queue comprising a plurality of cache window lists, each of the plurality of cache window lists configured to store one or more pointers to one or more cache windows.

2. The computer apparatus of claim 1 , wherein each of the one or more cache window lists comprises a hash table.

3. The computer apparatus of claim 1 , wherein:

the computer executable program code is further configured to determine a cache window list in the current temporal queue based on a feature of the input output/output operation; and

adding the identified cache window to the current temporal queue comprises adding the identified cache window to the determined cache window list.

4. The computer apparatus of claim 3 , wherein the feature of the input/output operation comprises a number of cache lines accessed during the input/output operation.

5. The computer apparatus of claim 1 , wherein:

each of the prior temporal queue and current temporal queue are defined by a threshold number of input/output operations; and

the computer executable program code is further configured to increment a counter of input/output operations.

6. The computer apparatus of claim 5 , wherein the computer executable program code is further configured to alter the threshold number of input/output operations.

7. A data storage system, comprising:

a processor;

one or more data storage elements connected to the processor;

memory connected to the processor, at least a portion of the memory comprising a cache for the one or more data storage elements; and

computer executable program code configured to execute on the processor,

wherein the computer executable program code is configured to:

receive an input/output operation directed toward data in the cache;

identify a cache window associated with data to be accessed pursuant to the input/output operation;

remove the cache window from a prior temporal queue; and

add the cache window to a current temporal queue comprising a plurality of cache window lists, each of the plurality of cache window lists configured to store one or more pointers to one or more cache windows.

8. The data storage system of claim 7 , wherein each of the one or more cache window lists comprises a hash table.

9. The data storage system of claim 7 , wherein:

the computer executable program code is further configured to determine a cache window list in the current temporal queue based on a feature of the input/output operation; and

adding the identified cache window to the current temporal queue comprises adding the identified cache window to the determined cache window list.

10. The data storage system of claim 9 , wherein the feature of the input/output operation comprises a number of cache lines accessed during the input/output operation.

11. The data storage system of claim 7 , wherein:

each of the prior temporal queue and current temporal queue are defined by a threshold number of input/output operations; and

the computer executable program code is further configured to increment a counter of input/output operations.

12. The data storage system of claim 11 , wherein the computer executable program code is further configured to alter the threshold number of input/output operations.

13. A method for maintaining hot data in a data storage system cache, comprising:

receiving an input/output operation directed toward data in a cache;

identifying a cache window associated with the data in the cache;

removing the cache window from a prior temporal queue; and

adding the cache window to a current temporal queue comprising a plurality of cache window lists, each of the plurality of cache window lists configured to store one or more pointers to one or more cache windows.

14. The method of claim 13 , further comprising:

determining a cache window list in the current temporal queue based on a feature of the input/output operation,

wherein adding the identified cache window to the current temporal queue comprises adding the identified cache window to the determined cache window list.

15. The method of claim 14 , wherein the feature of the input/output operation comprises a number of cache lines accessed during the input/output operation.

16. The method of claim 13 , further comprising:

incrementing a counter of input/output operations,

wherein each of the prior temporal queue and current temporal queue are defined by a threshold number of input/output operations.

17. The method of claim 16 , further comprising altering the threshold number of input/output operations.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2014
From: SHIVASHANKARAIAH, VINAY BANGALORE; THILLAI, KUMARAVEL
To: LSI CORPORATION
Reel/Frame 032880/0300 →
Priority Claims (1)
IN 527KOL2014 · May 9, 2014 · national
Continuity (1)
Related Publication 20150324295A1 · Nov 12, 2015