Semiconductor device
View Patent ↗A device includes a semiconductor substrate, a first penetrating electrode penetrating through the semiconductor substrate, a first test pad, and a first tri-state buffer coupled between the first penetrating electrode and the first test pad. The first tri-state buffer receives a buffer control signal at a control terminal thereof. The device further includes a buffer control circuit supplying the buffer control signal to the first tri-state buffer.
1. A semiconductor device comprising:
a semiconductor substrate;
a plurality of electrodes extending from a front side of the semiconductor substrate to an opposite side of the semiconductor substrate;
a plurality of pads on the front side of the semiconductor substrate;
a plurality of tri-state buffers coupled between respective ones of the plurality of electrodes and respective ones of the plurality of pads;
a first input pad on the front side of the semiconductor substrate configured to receive a first input signal; and
a buffer controller configured to receive the first input signal and to provide a buffer control signal to the plurality of tri-state buffers, wherein the buffer control signal is configured to activate the plurality of tri-state buffers to electrically connect respective ones of the plurality of electrodes with respective ones of the plurality of pads during a time in which the first input signal has an active level.
2. The semiconductor device of claim 1 , wherein the plurality of pads are test pads.
3. The semiconductor device of claim 1 , wherein the buffer controller comprises a set/reset flip-flop circuit.
4. The semiconductor device of claim 3 , wherein the first input pad is coupled to a set input of the set/reset flip-flop.
5. The semiconductor device of claim 4 , comprising a second input pad configured to receive a second input signal, wherein the second input pad is coupled to a reset input of the set/reset flip-flop.
6. The semiconductor device of claim 5 , comprising an additional electrode extending from the front side of the semiconductor substrate to the opposite side of the semiconductor substrate, wherein the additional electrode is coupled to the second input pad.
7. The semiconductor device of claim 4 , comprising a resistor coupled between the set input of the set/reset flip-flop and a power supply potential.
8. The semiconductor device of claim 7 , wherein the power supply potential is VDD.
9. The semiconductor device of claim 1 , wherein each electrode of the plurality of electrodes is a data terminal.
10. The semiconductor device of claim 9 , wherein each tri-state buffer of the plurality of tri-state buffers is a bidirectional tri-state buffer.
11. The semiconductor device of claim 1 , wherein each electrode of the plurality of electrodes is a selected one of a clock, an address, and a command terminal.
12. The semiconductor device of claim 11 , wherein each tri-state buffer of the plurality of tri-state buffers is a tri-state output buffer.
13. The semiconductor device of claim 1 , wherein the first input signal has a low level when active.
14. The semiconductor device of claim 1 , wherein the first input pad is coupled to an input of an AND gate.
15. A semiconductor device comprising:
a semiconductor substrate;
an electrode extending from a front side of the semiconductor substrate to an opposite side of the semiconductor substrate;
a pad on the front side of the semiconductor substrate;
a tri-state buffer coupled between the electrode and the pad;
a first input pad on the front side of the semiconductor substrate configured to receive a first input signal; and
a buffer controller configured to receive the first input signal and to provide a buffer control signal to the tri-state buffer, wherein the buffer control signal is configured to activate the tri-state buffer to electrically connect the electrode with the pad during a time in which the first input signal has an active level.
16. The semiconductor device of claim 15 , wherein the pad is a test pad.
17. The semiconductor device of claim 15 , wherein the buffer controller comprises a set/reset flip-flop circuit.
18. The semiconductor device of claim 15 , wherein the tri-state buffer is a bidirectional tri-state buffer.
19. The semiconductor device of claim 15 , wherein the tri-state buffer is a tri-state output buffer.