IP Library Granted Patent US 9,197,460
Granted Patent B1
US 9,197,460 · App. 14/288,838 · Granted Nov 24, 2015

Slicer trim methodolgy and device

Inventors: Vladimir Sindalovsky (Warrington, PA); Lane A. Smith (Easton, PA); Niall Fitzgerald (Dublin, IR)
Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
H04L25/03159H04L25/03057H04L25/03312H04L27/01H04L2025/03592
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Quick Facts
Patent No.
US 9,197,460
App. No.
14/288,838
Granted
Nov 24, 2015
Kind
B1
Abstract

Described embodiments provide for, in a receiver circuit employing a data latch, circuitry to adjust trim offset of the data latch to account for latch functional features (e.g., hysteresis and metastability) that may interact with trim of the latch. In accordance with the described embodiments, a trim procedure runs in a pre-selected directions of offset voltage ramp in order to average out the effect of hysteresis and metastability on the final trim offset choice. Different thresholds for accumulated slicer “0” and “1” discrimination of the circuitry to adjust trim offset allows for significant reduction in the number of trim runs, accelerating the slicers' trim process allowing for relatively quick determination of trim offset whenever the slicers are idle.

Claims (67)

1. A method of generating a trim offset in a decision device, the method comprising:

applying a signal including a sequence of equivalent data values to the decision device;

initializing a trim offset value to a first trim value, the trim offset value applied to the decision device to set a decision threshold for the decision device;

varying the trim offset value over a range of trim values defined by the first trim value and a second trim value;

generating an inconclusive region by, for each of the trim values:

accumulating at least one output value of the decision device,

comparing the accumulated output value of the decision device to a high threshold and a low threshold, and

classifying, as conclusive or inconclusive, a current value of the trim offset value corresponding to each data value based on the comparison; and

determining a desired trim offset value as the trim value about a center of the inconclusive region.

2. The method of claim 1 , wherein the generating an inconclusive region comprises:

varying the trim offset value from the first trim value to the second trim value in the range of trim values; and

for each of the trim values:

accumulating a plurality of output values of the decision device and providing an averaged output value;

comparing the averaged output value to the high threshold and the low threshold;

classifying, as conclusive, the current trim offset value if the averaged output value i) reaches or exceeds the high threshold or ii) reaches or falls below the low threshold; and

classifying, as inconclusive, the current trim offset value if the averaged output value is between the high threshold and the low threshold.

3. The method of claim 1 , comprising:

varying the trim offset value from the first trim value to the second trim value and varying the range of trim values defined by a third trim value to a fourth trim value;

wherein the step of determining a desired trim offset value comprises averaging at least two trim offset values about the center of the inconclusive region.

4. The method of claim 3 , wherein the first trim value is less than the second trim value, and the fourth trim value is less than the third trim value.

5. The method of claim 4 , wherein the first trim value and the fourth trim value are equivalent, and the second trim value and the third trim value are equivalent.

6. The method of claim 1 , wherein the method is embodied in a Serializer/Deserializer (SerDes) device.

7. Apparatus for generating a trim offset, the apparatus comprising:

a decision device receiving a signal including a sequence of equivalent data values;

a logic circuitry configured to initialize a trim offset value to a first trim value, the trim offset value applied to the decision device to set a decision threshold for the decision device;

the logic circuitry configured to vary the trim offset value over a range of trim values defined by the first trim value to a second trim value;

the logic circuitry configured to generate an inconclusive region by, for each of the trim values:

accumulating at least one output value of the decision device,

comparing the accumulated output value of the decision device to a high threshold and a low threshold, and

classifying, as conclusive or inconclusive, a current value of the trim offset value corresponding to each data value based on the comparison; and

the logic circuitry configured to determine a desired trim offset value as the trim offset value corresponding to the data value in the sequence about the center of the inconclusive region.

8. The apparatus of claim 7 , wherein the logic circuitry is configured to generate an inconclusive region by:

varying the trim offset value from the first trim value to the second trim value in the range of trim values; and

the logic circuitry comprises an accumulator, a discriminator and a state machine, and wherein, for each of the trim values:

accumulator accumulates a plurality of output values of the decision device and provides an averaged output value;

the discriminator compares the averaged output value to the high threshold and the low threshold; and

the state machine classifies, as conclusive, the current trim offset value if the averaged output value i) reaches or exceeds the high threshold or ii) reaches or falls below the low threshold; and classifies, as inconclusive, the current trim offset value if the averaged output value is between the high threshold and the low threshold.

9. The apparatus of claim 7 , wherein the logic circuitry is configured to:

vary the trim offset value from the first trim value to the second trim value and vary the range of trim values defined by a third trim value to a fourth trim value;

wherein the logic circuitry is configured to determine a desired trim offset value by averaging at least two trim offset values about the center of the inconclusive region.

10. The apparatus of claim 9 , wherein the first trim value is less than the second trim value, and the fourth trim value is less than the third trim value.

11. The apparatus of claim 10 , wherein the first trim value and the fourth trim value are equivalent, and the second trim value and the third trim value are equivalent.

12. The apparatus of claim 7 , wherein the decision device is a latch.

13. The apparatus of claim 12 , wherein the latch is a sense amplifier.

14. The apparatus of claim 7 , wherein the apparatus is embodied in a Serializer/Deserializer (SerDes) device.

15. The apparatus of claim 7 , wherein the apparatus is embodied in an integrated circuit.

16. A non-transitory machine-readable storage medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method for generating a trim offset in a decision device, comprising the steps of:

applying a signal including a sequence of equivalent data values to the decision device;

initializing a trim offset value to a first trim value, the trim offset value applied to the decision device to set a decision threshold for the decision device;

varying the trim offset value over a range of trim values defined by the first trim value and a second trim value;

generating an inconclusive region by, for each of the trim values:

accumulating at least one output value of the decision device,

comparing the accumulated output value of the decision device to a high threshold and a low threshold, and

classifying, as conclusive or inconclusive, a current value of the trim offset value corresponding to each data value based on the comparison; and

determining a desired trim offset value as the trim value about a center of the inconclusive region.

17. The method of claim 16 , wherein the generating an inconclusive region comprises:

varying the trim offset value from the first trim value to the second trim value in the range of trim values; and

for each of the trim values:

accumulating a plurality of output values of the decision device and providing an averaged output value;

comparing the averaged output value to the high threshold and the low threshold;

classifying, as conclusive, the current trim offset value if the averaged output value i) reaches or exceeds the high threshold or ii) reaches or falls below the low threshold; and

classifying, as inconclusive, the current trim offset value if the averaged output value is between the high threshold and the low threshold.

18. The method of claim 16 , comprising:

varying the trim offset value from the first trim value to the second trim value and varying the range of trim values defined by a third trim value to a fourth trim value;

wherein the step of determining a desired trim offset value comprises averaging at least two trim offset values about the center of the inconclusive region.

19. The method of claim 18 , wherein the first trim value is less than the second trim value, and the fourth trim value is less than the third trim value.

20. The method of claim 19 , wherein the first trim value and the fourth trim value are equivalent, and the second trim value and the third trim value are equivalent.

Assignments (8)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2014
From: SINDALOVSKY, VLADIMIR; SMITH, LANE A.; FITZGERALD, NIALL
To: LSI CORPORATION
Reel/Frame 032976/0516 →
Continuity (1)
Provisional Application 61987639 · May 2, 2014