Decoupling host and device address maps for a peripheral component interconnect express controller
View Patent ↗A controller includes a virtual memory mapped to device-side Peripheral component interconnect express address space includes virtual buffers allocation for each data transfer. Each virtual buffer is associated with a scatter/gather list entry in a host memory. The controller executes direct transfers between Peripheral component interconnect express devices and host memory without introducing address mapping dependencies between the host and device domains.
1. A controller apparatus comprising:
one or more hardware engines;
memory connected to the one or more hardware engines;
one or more host ports connected to the one or more hardware engines, configured to connect to one or more host devices; and
one or more device ports connected to the one or more hardware engines, configured to connect to one or more peripheral component interconnect express devices,
wherein the one or more hardware engines are configured to:
determine a transaction size;
allocate a buffer header;
allocate a virtual buffer, associated with one or more memory addresses in the peripheral component interconnect device, in a virtual memory according to the transaction size;
associate the virtual buffer with the buffer header;
associate the virtual buffer with a scatter/gather list element, associated with a memory address in a host; and
link the buffer header and the scatter/gather list element in a state table entry.
2. The controller apparatus of claim 1 , wherein the one or more hardware engines are further configured to place the buffer header in a buffer header list.
3. The controller apparatus of claim 2 , wherein the one or more hardware engines are further configured to organize the buffer header list according to a hash function.
4. The storage device of claim 2 , wherein the buffer header list is organized as a hash table.
5. The controller apparatus of claim 1 , wherein the one or more hardware engines are further configured to translate a SCSI transaction into a PCIe device transaction.
6. The controller apparatus of claim 5 , wherein the one or more hardware engines are further configured to issue the translated transaction to the peripheral component interface device.
7. The controller apparatus of claim 1 , wherein the one or more hardware engines are further configured to pull a SCSI input/output and a scatter/gather list into a local memory.
8. A method for mapping peripheral component interconnect device addresses to host addresses, comprising:
determining a transaction size;
allocating a buffer header;
allocating a virtual buffer in a virtual memory according to the transaction size;
associating the virtual buffer with the buffer header;
associating the virtual buffer with a scatter/gather list element, wherein:
the virtual buffer is associated with one or more virtual memory addresses provided to the peripheral component interconnect device; and
the scatter/gather list entry is associated with a memory address in the host; and
linking the buffer header and scatter/gather list element in a state table entry.
9. The method of claim 8 , further comprising placing the buffer header in a buffer header list.
10. The method of claim 9 , further comprising organizing the buffer header list according to a hash function.
11. The method of claim 8 , further comprising translating a host transaction into a PCIe device transaction.
12. The method of claim 11 , further comprising issuing the translated fast path transaction to the peripheral component interface device.
13. The method of claim 8 , further comprising pulling a SCSI input/output and a scatter/gather list into a local memory.
14. A redundant array of independent disks data storage device comprising:
a plurality of peripheral component interconnect data storage devices; and
a controller configured to control access between the plurality of peripheral component interconnect data storage devices and one or more hosts, comprising:
one or more hardware engines;
memory connected to the one or more hardware engines;
one or more host ports connected to the one or more hardware engines, configured to connect to one or more host devices; and
one or more device ports connected to the one or more hardware engines and connected to the one or more peripheral component interconnect express devices, wherein:
the one or more hardware engines are configured to:
determine a transaction size;
allocate a buffer header;
allocate a virtual buffer, associated with one or more memory addresses in the peripheral component interconnect device, in a virtual memory according to the transaction size;
associate the virtual buffer with the buffer header;
associate the virtual buffer with a scatter/gather list element, associated with a memory address in a host; and
link the buffer header and scatter/gather list entry in a state table.
15. The storage device of claim 14 , wherein the one or more hardware engines are further configured to place the buffer header in a buffer header list.
16. The storage device of claim 15 , wherein the one or more hardware engines are further configured to organize the buffer header list according to a hash function.
17. The storage device of claim 15 , wherein the buffer header list is organized as a hash table.
18. The storage device of claim 14 , wherein the one or more hardware engines are further configured to translate a host-originated transaction into a PCIe device transaction.
19. The storage device of claim 18 , wherein the one or more hardware engines are further configured to issue the translated transaction to the peripheral component interface device.
20. The storage device of claim 14 , wherein the one or more hardware engines are further configured to pull SCSI input/output and a scatter/gather list into a local memory.