Semiconductor device and semiconductor device fabrication method
A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.
1. A semiconductor device comprising:
a first insulating layer;
a first wiring formed in the first insulating layer;
a second wiring formed in the first insulating layer and separated from the first wiring;
a second insulating layer formed over the first insulating layer;
a via formed in the second insulating layer and connected to the first wiring;
a third wiring formed in the second insulating layer, and connected to the via at a portion of the third wiring; and
a first nick portion located at an outer edge of the third wiring beside the portion of the third wiring; wherein
the first wiring and a first part of the second wiring overlap with the third wiring in a plan view.
2. The semiconductor device according to claim 1 , wherein:
the outer edge includes a first outer edge portion;
the first outer edge portion includes the first nick portion;
the outer edge includes a second outer edge portion that is opposite to the first nick portion;
the portion of the third wiring is located between the second outer edge portion and the first nick portion;
the second outer edge portion intersects the first outer edge portion;
a third outer edge portion that is opposite to the first outer edge portion and that intersects the second outer edge portion; and
a first distance between the first nick portion and the second outer edge portion is shorter than a second distance between the first outer edge portion and the third outer edge portion.
3. The semiconductor device according to claim 2 , wherein the first distance is 1 μm or less.
4. The semiconductor device according to claim 2 , wherein the via is formed in a region within 0.1 μm from the first outer edge portion in a direction from the first outer edge portion to the third outer edge portion.
5. The semiconductor device according to claim 2 , wherein length of the first nick portion in a direction from the first outer edge portion to the third outer edge portion is 0.25 μm or more.
6. The semiconductor device according to claim 1 , wherein:
the outer edge includes a second nick portion;
the second edge portion is located opposite to the first nick portion; and
the portion of the third wiring is located between the first nick portion and the second nick portion.
7. The semiconductor device according to claim 6 , wherein:
the outer edge includes a first outer edge portion;
the first outer edge portion includes the first nick portion and the second nick portion;
the outer edge includes a third outer edge portion opposite the first outer edge portion; and
a third distance between the first nick portion and the second nick portion is shorter than a second distance between the first outer edge portion and the third outer edge portion.
8. The semiconductor device according to claim 7 , wherein the third distance is 1 μm or less.
9. The semiconductor device according to claim 7 , wherein the via is formed in a region within 0.1 μm from the first outer edge portion in a direction from the first outer edge portion to the third outer edge portion.
10. The semiconductor device according to claim 7 , wherein length of the first nick portion and length of the second nick portion in a direction from the first outer edge portion to the third outer edge portion are 0.25 μm or more.
11. The semiconductor device according to claim 1 , wherein the second wiring is formed adjacently to the first wiring in the first insulating layer.
12. The semiconductor device according to claim 1 , wherein a second part of the second wiring overlaps with the first nick portion in a plan view.
13. The semiconductor device according to claim 1 , wherein the first nick portion is located beside the via.