Semiconductor device and manufacturing method thereof
A first well in a first conductivity type which is formed at a first region and is electrically connected to a first power supply line, a second well in a second conductivity type being an opposite conductivity type of the first conductivity type which is formed at a second region and is electrically connected to a second power supply line, a third well in the second conductivity type which is integrally formed with the second well at a third region adjacent to the second region, a fourth well in the first conductivity type integrally formed with the first well at a fourth region adjacent to the first region, a fifth well in the first conductivity type which is formed at the third region to be shallower than the third well, and a sixth well in the second conductivity type which is formed at the fourth region to be shallower than the fourth well, are included.
1. A semiconductor device, comprising:
a semiconductor substrate that includes a first region, a second region, a third region and a fourth region;
a first power supply line;
a second power supply line; and
a logic cell that includes
an input terminal,
an output terminal,
a first well of a first conductivity type formed in the first region of the semiconductor substrate and electrically connected to the first power supply line,
a second well of a second conductivity type that is an opposite conductivity type of the first conductivity type formed the second region of the semiconductor substrate and electrically connected to the second power supply line,
a third well of the second conductivity type formed in the third region of the semiconductor substrate;
a fourth well of the first conductivity type formed in the fourth region of the semiconductor substrate;
a fifth well of the first conductivity type formed in the third region and located shallower than the third well;
a sixth well of the second conductivity type formed in the fourth region and located shallower than the fourth well,
a first complementary transistor pair that is electrically connected to the input terminal,
a first transistor of the first complementary transistor pair includes a first source/drain region of the second conductivity type formed in the first well and a first gate electrode,
a second transistor of the first complementary transistor pair includes a second source/drain region of the first conductivity type formed in the second well and a second gate electrode,
a second complementary transistor pair that is electrically connected to the output terminal,
a third transistor of the second complementary transistor pair includes a third source/drain region of the second conductivity type formed in the fifth well and a third gate electrode that is electrically connected to the fifth well through a first electric conductor, and
a fourth transistor of the second complementary transistor pair includes a fourth source/drain region of the first conductivity type formed in the sixth well and a fourth gate electrode that is electrically connected to the sixth well through a second electric conductor.
2. The semiconductor device according to claim 1 , wherein:
the third region is adjacent to the second region;
the fourth region is adjacent to the first region;
the third well is connected to the second well;
the fourth well is connected to the first well.
3. The semiconductor device according to claim 1 ,
wherein the logic cell is a buffer circuit, an AND circuit, an OR circuit, or a flipflop circuit.
4. The semiconductor device according to claim 1 ,
wherein the first complementary transistor pair includes a first output node,
the first output node is electrically connected to the third gate electrode and the fourth gate electrode.
5. The semiconductor device according to claim 4 ,
wherein the first output node is electrically connected to the first source/drain region and the second source/drain region.