Memory system and control method therefor
A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.
1. A method for adjusting output, timing of a plurality of memory devices, the method comprising the steps of:
providing a clock signal to each of the plurality of memory devices, wherein each one of the plurality of memory devices delays the clock signal in a respective variable delay circuit to provide a respective output clock signal;
sequentially issuing read commands to each of the plurality of memory devices, whereby each one of the plurality of memory devices provides read data in synchronization with the respective output clock signal;
receiving read data from each of the plurality of memory devices;
determining a respective delay time for each of the plurality of memory devices, wherein the respective delay time is indicative of an elapsed period between a time at which the read command is issued to the respective memory device and a time at which the read data is provided by the respective memory device;
identifying a slowest memory device as the memory device having the longest delay time; and
adjusting the respective variable delay circuit in each of the plurality of memory devices other than the slowest memory device so as to make the delay time for the memory device substantially the same as the delay time of the slowest memory device.
2. The method of claim 1 wherein the plurality of memory devices are stacked.
3. The method of claim 2 wherein the plurality of memory devices are interconnected by through electrodes.
4. The method of claim 1 wherein the plurality of memory devices are dynamic random access memory devices.
5. The method of claim 1 wherein adjusting the respective variable delay circuit in each of the plurality of memory devices comprises issuing a setting command.
6. The method of claim 5 wherein the setting command comprises an up/down signal.
7. The method of claim 6 wherein the step of issuing the setting command is repeated until the delay time of the respective memory device is substantially the same as the delay time of the slowest memory device.
8. The method of claim 5 wherein the setting command comprises an adjustment code.
9. The method of claim 1 wherein variable delay circuit comprises a register specifying a period by which the variable delay circuit is to delay the clock signal of the respective memory device.
10. The method of claim 9 wherein the register is non-volatile.
11. The method of claim 1 wherein the output timing of the plurality of memory devices is adjusted responsive to a power source being turned on.
12. The method of claim 1 wherein the output timing of the plurality of memory devices is adjusted responsive to determining that a reset has been performed.