ELIMINATING SYSTEMATIC IMBALANCES AND REDUCING CIRCUIT PARAMETER VARIATIONS IN HIGH GAIN AMPLIFIERS

1 . A method for reducing variations and mismatch in circuit parameters of an amplifier circuit, said method comprising:

removing an offset between at least one current source and at least one current sink in an amplifier circuit via a bias generation component; and

ensuring that all components associated with said amplifier circuit are in saturation at a quiescent point across varying operating conditions of said amplifier circuit so as to relax the design of feedback loops employed to regulate common mode levels at high impedance nodes within said amplifier circuit.

2 . The method of claim 1 further comprising:

configuring said amplifier circuit to include at least one current summing node; and

employing a copy of a branch of said amplifier circuit and at least one previously generated bias voltage to generate a bias voltage for a final current source at said at least one current summing node.

3 . The method of claim 1 further comprising wiring a high impedance node in a bias generator of said amplifier circuit such that all devices in said bias generator are in saturation across process, voltage, and temperature.

4 . The method of claim 1 further comprising matching a copy of at least one branch of said amplifier circuit to a main amplifier of said amplifier circuit.

5 . The method of claim 1 further comprising configuring said amplifier circuit such that P current sources and N current sinks within said amplifier circuit track one another regardless of absolute mirroring accuracy with respect to a master reference circuit.

6 . A degeneration method for use in reducing variations in amplifier circuits, said method comprising:

configuring an amplifier circuit to include at least one gain stage that employs degeneration with a degeneration factor; and

reducing a variation in transconductance of said at least one gain stage by rendering said degeneration factor invariant to changes in operating conditions of said amplifier circuit, such that a resulting reduction in gain variation translates to a reduced spread in system level parameters.

7 . The method of claim 6 further comprising configuring said amplifier circuit with a tight spread in circuit parameters including at least bandwidth and phase shifts associated with said amplifier circuit.

8 . The method of claim 6 further comprising incorporating said at least one gain stage into a closed loop amplifier circuit within said amplifier circuit, so as to reduce gain variation thereof.

9 . The method of claim 6 further comprising configuring said amplifier circuit to include transistors of the same type as differential pair elements of said at least one gain stage for degeneration.

10 . The method of claim 6 further comprising configuring said at least one gain stage to include at least one degeneration device that is split into two equal halves.

11 . The method of claim 10 further comprising a gate of one half of said two equal halves of said at least one degeneration device with a positive input and the other half of said two equal halves of said at least one degeneration device with a negative input.

12 . An apparatus for reducing variations and mismatch in circuit parameters of an amplifier circuit, said apparatus comprising:

at least one current source and at least one current sink in an amplifier circuit, wherein an offset between said at least one current source and said at least one current sink in said amplifier circuit is removed via a bias generation component; and

wherein all components associated with said amplifier circuit are in saturation at a quiescent point across varying operating conditions of said amplifier circuit so as to minimize feedback loops employed to regulate common mode levels at high impedance nodes within said amplifier circuit.

13 . The apparatus of claim 12 wherein said amplifier circuit further comprises:

at least one current summing node; and

wherein a copy of a branch of said amplifier circuit and at least one previously generated bias voltage are employed by said amplifier circuit to generate a bias voltage for a final current source at said at least one current summing node.

14 . The apparatus of claim 12 further comprising a high impedance node wired in a bias generator of said amplifier circuit such that all devices in said bias generator are in saturation across process, voltage, and temperature.

15 . The apparatus of claim 12 wherein a copy of at least one branch of said amplifier circuit is matched to a main amplifier of said amplifier circuit.

16 . The apparatus of claim 12 wherein said amplifier circuit is configured such that P current sources and N current sinks within said amplifier circuit track one another regardless of absolute mirroring accuracy with respect to a master reference circuit.

17 . An apparatus for reducing variations in amplifier circuits, said apparatus comprising:

an amplifier circuit comprising at least one gain stage that employs degeneration with a degeneration factor, wherein a variation in transconductance of said at least one gain stage is reduced by rendering said degeneration factor invariant to changes in operation conditions of said amplifier circuit, such that a resulting reduction in gain variation translates to a reduced spread in system level parameters.

18 . The apparatus of claim 17 wherein said amplifier circuit is configured with a tight spread in circuit parameters including at least bandwidth and phase shifts associated with said amplifier circuit.

19 . The apparatus of claim 17 wherein said at least one gain stage is incorporated into a closed loop amplifier circuit within said amplifier circuit, so as to reduce gain variation thereof.

20 . The apparatus of claim 17 wherein said amplifier circuit further comprises transistors of the same type as differential pair elements of said at least one gain stage for degeneration.