IP Library Granted Patent US 9,514,684
Granted Patent B2
US 9,514,684 · App. 14/331,612 · Granted Dec 6, 2016

Display driver

Inventors: Keita Tsubakino (Tokyo, JP); Kiichi Makuta (Tokyo, JP); Toshikazu Arai (Tokyo, JP); Yoshinori Ura (Tokyo, JP)
Assignee: Synpatics Display Devices GK
G09G3/3275G09G2310/0289G09G2360/18G09G2370/08
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,514,684
App. No.
14/331,612
Granted
Dec 6, 2016
Kind
B2
Abstract

A gradation voltage corresponding to a display data is input to a signal electrode driving circuit. The signal electrode driving circuit includes a voltage output circuit which outputs a drive voltage corresponding to the input gradation voltage, and a slew rate assist circuit which accelerates a transition of an output voltage of the voltage output circuit. The slew rate assist circuit accelerates the transition of the output voltage after a predetermined time from a start of transition of the gradation voltage.

Claims (47)

1. A display driver comprising:

a plurality of drive terminals which are coupled to signal electrodes of a display panel; and

a signal electrode driving circuit,

wherein the signal electrode driving circuit includes a plurality of source amplifiers which are respectively coupled to the plurality of drive terminals, receive a gradation voltage corresponding to display data, and output a drive voltage corresponding to the gradation voltage to the drive terminals,

wherein the source amplifier includes a voltage output circuit which outputs the drive voltage corresponding to an input gradation voltage, and a slew rate assist circuit which accelerates a transition of the output drive voltage of the voltage output circuit, wherein the slew rate assist circuit starts the acceleration after a predetermined time from the start of transition of the output voltage, and the transition starts in response to a start transition of the gradation voltage,

wherein the voltage output circuit includes a positive polarity side output transistor, a negative polarity side output transistor, and a first amplification circuit, the positive polarity side output transistor is coupled between a positive polarity side power supply and a drive terminal, the negative polarity side output transistor is coupled between a negative polarity side power supply and the drive terminal, and the first amplification circuit receives the gradation voltage and outputs a positive polarity side control signal which controls a control electrode of the positive polarity side output transistor and a negative polarity side control signal which controls a control electrode of the negative polarity side output transistor,

wherein the slew rate assist circuit is configured so as to enable transitions of the positive polarity side control signal and the negative polarity side control signal to be accelerated,

wherein the slew rate assist circuit receives a positive polarity side clock and a negative polarity side clock, controls whether or not to accelerate the transition of the positive polarity side control signal based on the positive polarity side clock, and controls whether or not to accelerate the transition of the negative polarity side control signal based on the negative polarity side clock, and

wherein the slew rate assist circuit starts the acceleration of the transition of the positive polarity side control signal after a period of a pulse width of the positive polarity side clock from the start of transition of the gradation voltage, and starts the acceleration of the transition of the negative polarity side control signal after a period of a pulse width of the negative polarity side clock from the start of transition of the gradation voltage.

2. The display driver according to claim 1 , further comprising:

a first register which designates the pulse width of the positive polarity side clock;

a first pulse width adjusting circuit which adjusts the pulse width of the positive polarity side clock based on a parameter which is stored in the first register;

a second register which designates the pulse width of the negative polarity side clock; and

a second pulse width adjusting circuit which adjusts the pulse width of the negative polarity side clock based on a parameter which is stored in the second register.

3. The display driver according to claim 2 ,

wherein the signal electrode driving circuit includes the plurality of source amplifiers, a plurality of gradation voltage selection circuits which are coupled to the plurality of source amplifiers and supply a plurality of gradation voltages with a plurality of potential levels to each of the plurality of source amplifiers, and a plurality of level shifters which are coupled to the plurality of gradation voltage selection circuits, convert levels of digital values of the display data and then supply the converted digital values to each of the plurality of gradation voltage selection circuits, and

wherein the plurality of gradation voltages are supplied to the plurality of gradation voltage selection circuits, and the gradation voltage selection circuits, based on the digital value of the display data which is supplied to each of them, select one potential level out of the plurality of gradation voltages supplied and supply the selected potential level to the coupled source amplifier.

4. The display driver according to claim 3 ,

wherein the plurality of source amplifiers, the plurality of gradation voltage selection circuits, and the plurality of level shifters are formed on same semiconductor substrate and have same pitch as the plurality of drive terminals.

5. The display driver according to claim 1 ,

wherein the signal electrode driving circuit includes the plurality of source amplifiers, a plurality of gradation voltage selection circuits which are coupled to the plurality of source amplifiers and supply a plurality of gradation voltages with a plurality of potential levels to each of the plurality of source amplifiers, and a plurality of level shifters which are coupled to the plurality of gradation voltage selection circuits, convert levels of digital values of the display data and then supply the converted digital values to each of the plurality of gradation voltage selection circuits, and

wherein the plurality of gradation voltages are supplied to the plurality of gradation voltage selection circuits, and the gradation voltage selection circuits, based on the digital value of the display data which is supplied to each of them, select one potential level out of the plurality of gradation voltages supplied and supply the selected potential level to the coupled source amplifier.

6. The display driver according to claim 5 ,

wherein the plurality of source amplifiers, the plurality of gradation voltage selection circuits, and the plurality of level shifters are formed on same semiconductor substrate and have same pitch as the plurality of drive terminals.

7. A display driver comprising:

a plurality of drive terminals which are coupled to signal electrodes of a display panel; and

a signal electrode driving circuit,

wherein the signal electrode driving circuit includes a plurality of source amplifiers which are respectively coupled to the plurality of drive terminals, receive a gradation voltage corresponding to display data, and output a drive voltage corresponding to the gradation voltage to the drive terminals, and

wherein the source amplifier controls in such a way that a current drive capability with respect to the drive terminal during a first time period after an output start of the drive voltage is lower than a current drive capability with respect to the drive terminal during a second time period before the drive voltage reaches a drive voltage corresponding to the gradation voltage after the first time period,

wherein the source amplifier includes a voltage output circuit which outputs the drive voltage corresponding to the input gradation voltage, and a slew rate assist circuit which accelerates a transition of an output voltage of the voltage output circuit,

wherein the source amplifier stops the slew rate assist circuit during the first time period and operates the slew rate assist circuit during the second time period, and

wherein the display driver further comprises

a first register that when the transition of the output voltage rises, defines a length of the first time period during which the slew rate assist circuit stops; and

a second register that when the transition of the output voltage falls, defines the length of the first time period during which the slew rate assist circuit stops.

8. A display driver comprising:

a plurality of drive terminals which are coupled to signal electrodes of a display panel; and

a signal electrode driving circuit,

wherein the signal electrode driving circuit includes a plurality of source amplifiers which are respectively coupled to the plurality of drive terminals, receive a gradation voltage corresponding to display data, and output a drive voltage corresponding to the gradation voltage to the drive terminals,

wherein the source amplifier includes a voltage output circuit which outputs the drive voltage corresponding to an input gradation voltage, and a slew rate assist circuit which accelerates a transition of the output drive voltage of the voltage output circuit, wherein the slew rate assist circuit starts the acceleration after a predetermined time from the start of transition of the output voltage, and the transition starts in response to a start transition of the gradation voltage,

wherein the voltage output circuit includes a positive polarity side output transistor, a negative polarity side output transistor, and a first amplification circuit, the positive polarity side output transistor is coupled between a positive polarity side power supply and a drive terminal, the negative polarity side output transistor is coupled between a negative polarity side power supply and the drive terminal, and the first amplification circuit receives the gradation voltage and outputs a positive polarity side control signal which controls a control electrode of the positive polarity side output transistor and a negative polarity side control signal which controls a control electrode of the negative polarity side output transistor,

wherein the slew rate assist circuit is configured so as to enable transitions of the positive polarity side control signal and the negative polarity side control signal to be accelerated,

wherein the slew rate assist circuit receives a positive polarity side clock and a negative polarity side clock, controls whether or not to accelerate the transition of the positive polarity side control signal based on the positive polarity side clock, and controls whether or not to accelerate the transition of the negative polarity side control signal based on the negative polarity side clock,

wherein the slew rate assist circuit starts the acceleration of the transition of the positive polarity side control signal after a period of a pulse width of the positive polarity side clock from the start of transition of the gradation voltage, and starts the acceleration of the transition of the negative polarity side control signal after a period of a pulse width of the negative polarity side clock from the start of transition of the gradation voltage,

wherein the signal electrode driving circuit includes the plurality of source amplifiers, a plurality of gradation voltage selection circuits which are coupled to the plurality of source amplifiers and supply a plurality of gradation voltages with a plurality of potential levels to each of the plurality of source amplifiers, and a plurality of level shifters which are coupled to the plurality of gradation voltage selection circuits, convert levels of digital values of the display data and then supply the converted digital values to each of the plurality of gradation voltage selection circuits, and

wherein the plurality of gradation voltages are supplied to the plurality of gradation voltage selection circuits, and the gradation voltage selection circuits, based on the digital value of the display data which is supplied to each of them, select one potential level out of the plurality of gradation voltages supplied and supply the selected potential level to the coupled source amplifier.

9. The display driver according to claim 8 ,

wherein the plurality of source amplifiers, the plurality of gradation voltage selection circuits, and the plurality of level shifters are formed on same semiconductor substrate and have same pitch as the plurality of drive terminals.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2024
From: SYNAPTICS JAPAN GK
To: SYNAPTICS INCORPORATED
Reel/Frame 067793/0211 →
SECURITY INTEREST Recorded Sep 27, 2017
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 044037/0896 →
CHANGE OF NAME Recorded Aug 8, 2016
From: SYNAPTICS DISPLAY DEVICES GK
To: SYNAPTICS JAPAN GK
Reel/Frame 039710/0331 →
CHANGE OF NAME Recorded Jun 1, 2015
From: SYNAPTICS DISPLAY DEVICES KK
To: SYNAPTICS DISPLAY DEVICES GK
Reel/Frame 035799/0129 →
CHANGE OF NAME Recorded Dec 2, 2014
From: RENESAS SP DRIVERS INC.
To: SYNAPTICS DISPLAY DEVICES KK
Reel/Frame 034512/0678 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2014
From: TSUBAKINO, KEITA; MAKUTA, KIICHI; ARAI, TOSHIKAZU; URA, YOSHINORI
To: RENESAS SP DRIVERS INC.
Reel/Frame 033316/0626 →
Priority Claims (1)
JP 2013-147324 · Jul 16, 2013 · national
Continuity (1)
Related Publication 20150022562A1 · Jan 22, 2015