Semiconductor integrated circuit device
There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.
1. A semiconductor integrated circuit device comprising:
a memory cell including: a holding circuit which has a plurality of MOSFETs and a pair of input/output nodes and operates with a first voltage as an operating voltage; and a pair of transfer MOSFETs which are coupled to the input/output nodes respectively and whose gates receive a selection signal; and
a voltage generation circuit for generating a second voltage which is higher than the first voltage in terms of an absolute value,
wherein in response to a unique ID generation instruction, the second voltage is applied to the gates of the transfer MOSFETs, a third voltage is supplied to the input/output nodes via the transfer MOSFETs, and then the second voltage applied to the gates of the transfer MOSFETs is lowered to a voltage that is lower than the first voltage in terms of an absolute value.
2. The semiconductor integrated circuit device according to claim 1 , wherein the holding circuit is a latch circuit comprising the MOSFETs.
3. The semiconductor integrated circuit device according to claim 2 , wherein the third voltage is equal to the first voltage.
4. A semiconductor integrated circuit device comprising:
a plurality of memory cells arranged in a matrix, each of the memory cell comprising: a holding circuit which has a plurality of MOSFETs and a pair of input/output nodes and operates with a first voltage as an operating voltage; and a pair of transfer MOSFETs which are coupled to the input/output nodes respectively and whose gates receive a selection signal;
a plurality of word lines arranged in respective rows of the matrix and each coupled to gates of pairs of transfer MOSFETs in a plurality of memory cells arranged in a corresponding row;
a plurality of bit line pairs arranged in respective columns of the matrix and each coupled to pairs of transfer MOSFETs in a plurality of memory cells arranged in a corresponding column;
a row selection circuit for selecting a word line from among the word lines;
a column selection circuit for selecting a bit line pair from among the bit line pairs; and
a voltage generation circuit for generating a second voltage which is higher than the first voltage in terms of an absolute value,
wherein in response to a unique ID generation instruction, the second voltage is applied to the word line selected by the row selection circuit, a third voltage is applied to the bit line pair selected by the column selection circuit, and then the second voltage applied to the selected word line is lowered to a voltage that is lower than the first voltage in terms of an absolute value.
5. The semiconductor integrated circuit device according to claim 4 , wherein the holding circuit is a latch circuit comprising the MOSFETs.
6. The semiconductor integrated circuit device according to claim 5 , wherein the third voltage is equal to the first voltage.
7. The semiconductor integrated circuit device according to claim 6 , wherein the voltage generation circuit is a booster circuit for boosting the first voltage.
8. The semiconductor integrated circuit device according to claim 7 , further comprising a CPU for providing the unique ID generation instruction.