Information processing system including semiconductor device having self-refresh mode
A method for controlling termination impedance of a data terminal in a dynamic random access memory device includes receiving a mode register set command to set an operation mode to a first mode, setting the operation mode in a mode register to the first mode, receiving a self-refresh entry command, entering self-refresh mode, activating a first input buffer connected to a termination impedance control terminal, and receiving an impedance control signal at the first buffer, wherein the termination impedance of the data terminal is set to a first impedance value if the termination impedance control signal has a first level and the termination impedance of the data terminal is set to a second impedance value if the termination impedance control signal has a second level.
1. A method for controlling termination impedance of a data terminal in a dynamic random access memory device, said method comprising:
receiving a mode register set command to set an operation mode to a first mode;
setting the operation mode in a mode register to the first mode;
receiving a self-refresh entry command;
entering self-refresh mode;
wherein the self-refresh entry command is received through a command terminal and a clock enable terminal;
activating a first input buffer connected to a termination impedance control terminal; and
receiving an impedance control signal at the first input buffer, wherein the termination impedance of the data terminal is set to a first impedance value if the termination impedance control signal has a first level and the termination impedance of the data terminal is set to a second impedance value if the termination impedance control signal has a second level.
2. The method as claimed in claim 1 wherein the second impedance value is off.
3. The method as claimed in claim 2 wherein the first impedance value is in a range of 30Ω to 120Ω.
4. The method as claimed in claim 1 wherein the first level is a high level and the second level is a low level.
5. The method as claimed in claim 1 wherein the operation mode is received through an address terminal.
6. The method as claimed in claim 1 wherein the mode register set command and the self-refresh entry command are received synchronously with a clock signal received by a clock input buffer connected to a clock terminal.
7. The method as claimed in claim 6 wherein the clock input buffer is deactivated after entering self-refresh mode.
8. The method as claimed in claim 1 further comprising:
receiving a self-refresh exit command;
exiting self-refresh mode;
receiving a mode register set command indicative of a second operation mode;
setting the operation mode in a mode register to the second mode;
receiving a self-refresh entry command;
entering self-refresh mode; and
deactivating the first input buffer, wherein the termination impedance of the data terminal is set to off.
9. The method as claimed in claim 8 wherein the self-refresh exit command is received through a clock enable terminal.