IP Library Granted Patent US 9,143,133
Granted Patent B2
US 9,143,133 · App. 14/469,894 · Granted Sep 22, 2015

Output apparatus, output driver, and level shifting system

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Quick Facts
Patent No.
US 9,143,133
App. No.
14/469,894
Granted
Sep 22, 2015
Kind
B2
Abstract

An output driver for driving a pad includes a pull-up circuit and a pull-down circuit. The pull-up circuit includes first, second and third first-type transistors. The first and second first-type transistors are commonly controlled by a first logic signal. The third first-type transistor is connected in parallel to the second first-type transistor. The pull-down circuit includes first, second and third second-type transistors. The first and second second-type transistors are commonly controlled by a second logic signal. The third second-type transistor is connected in parallel to the second second-type transistor. The pull-up circuit is configured such that a response speed of the first first-type transistor to the first logic signal is lower than that of the second first-type transistor to the first logic signal.

Claims (13)

1. An output apparatus, comprising:

a high level shifting circuit, configured to shift an input signal to a high output signal, the input signal having two input logic levels, the high output signal is at one of two different high output logic levels;

a high buffer circuit, configured to drive a high control node according to the high output signal;

a low level shifting circuit, configured to shift the input signal to a low output signal, the low output signal is at one of two different low output logic levels;

a low buffer circuit, configured to drive a low control node according to the low output signal; and

an output driver, comprising the high control node and the low control node, configured to drive a pad;

wherein, the two low output logic levels are the same as the two input logic levels.

2. The output apparatus according to claim 1 , wherein the two high output logic levels are respectively voltages of a high power line and a first power line, the two low output logic levels are respectively voltages of a low power line and a second power line, and the output driver is powered by the high power line and the low power line.

3. The output apparatus according to claim 1 , wherein the high level shifting circuit and the low level shifting circuit provide a non-overlapping function.

4. The output apparatus according to claim 1 , wherein a falling voltage change rate of the high output signal is smaller than a falling voltage change rate of the low output signal.

5. The output apparatus according to claim 1 , wherein a rising voltage change rate of the high output signal is greater than a rising voltage change rate of the low output signal.

6. The output apparatus according to claim 1 , wherein a bias providing circuit provides a reference bias to the high level shifting circuit to control a lower of the two high output logic levels.

7. The output apparatus according to claim 1 , wherein a bias providing circuit provides a reference bias to the low level shifting circuit to control a higher of the two low output logic levels.

Assignments (2)
MERGER Recorded Oct 8, 2019
From: MSTAR SEMICONDUCTOR, INC.
To: MEDIATEK INC.
Reel/Frame 050665/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2014
From: LIU, HSIAN-FENG; CHEN, CHUN-CHIA; CHEN, HSIN-KUANG; ZHANG, YAO-ZHONG
To: MSTAR SEMICONDUCTOR, INC.
Reel/Frame 033619/0315 →