IP Library Granted Patent US 9,407,291
Granted Patent B1
US 9,407,291 · App. 14/481,681 · Granted Aug 2, 2016

Parallel encoding method and system

Inventors: Hanan Weingarten (Herzelia, IL); Avi Steiner (Kiryat Motzkin, IL)
Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
H03M13/2703H03M13/2906H03M13/611
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Quick Facts
Patent No.
US 9,407,291
App. No.
14/481,681
Granted
Aug 2, 2016
Kind
B1
Abstract

A method for parallel multi-dimensional encoding, the method may include receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the data unit; selecting a first set of bits of the first version and a second set of bits of the second version; encoding, in parallel, the first set of bits and the second set of bits; wherein the encoding of the second set of bits is responsive to the second set of bits and a first redundancy result of the encoding of the first set of bits; and wherein the encoding of the first set of bits is responsive to the first set of bits and to a second redundancy result of the encoding of the second set of bits.

Claims (46)

1. A method for parallel multi-dimensional encoding, the method comprises:

receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the data unit;

selecting a first set of bits of the first version and a second set of bits of the second version;

encoding, in parallel, the first set of bits and the second set of bits;

wherein the encoding of the second set of bits is responsive to the second set of bits and a first redundancy result;

wherein the first redundancy result is calculated by applying an encoding process on a first payload that is associated with the first set of bits;

wherein the encoding of the first set of bits is responsive to the first set of bits and to a second redundancy result; and

wherein the second redundancy result is calculated by applying an encoding process on a second payload that is associated with the second set of bits.

2. The method according to claim 1 wherein first set of bits is a part of the first version and the second set of bits is a part of the second version.

3. The method according to claim 1 wherein first set of bits equals the first version and the second set of bits equals the second version.

4. The method according to claim 1 wherein at least one of the first set of bits and the second set of bits comprises data bits and does not include redundancy bits.

5. The method according to claim 1 wherein at least one of the first set of bits and the second set of bits does not include data bits and comprises redundancy bits.

6. The method according to claim 1 wherein each one of the first set of bits and the second set of bits does not include data bits and comprises redundancy bits.

7. The method according to claim 1 wherein the encoding of the second set of bits is executed by applying an encoding process that is associated with the second set of bits.

8. The method according to claim 1 wherein at least one of the first and second versions is an interleaved version of the group of bits.

9. The method according to claim 1 comprising selecting and the encoding until all first sets of bits of the first version are selected and encoded.

10. The method according to claim 1 comprising repeating the selecting and the encoding until only a part of all first sets of bits of the first version are selected and encoded.

11. The method according to claim 1 wherein the encoding, in parallel, of the first set of bits and the second set of bits generates a multi-dimensional codeword and comprises calculating redundancies that solving a linear equation system for computation of redundancies of the multi-dimensional codeword.

12. The method according to claim 1 wherein the encoding, in parallel, of the first set of bits and the second set of bits comprises:

receiving or generating multiple first estimated results of encoding of the first set of bits and multiple second estimated results of the encoding of the second set of bits;

finding, out of the multiple first and second estimated results, a pair of first and second estimated results that match outcomes of the encoding of the first set of bits and of the encoding of the second set of bits respectively.

13. The method according to claim 1 wherein the encoding, in parallel, comprises receiving or calculating a syndrome vector and a primitive element matrix; and creating an equation system for a vector of redundancy bits that represents an output of the encoding of the first and second sets of bits.

14. The method according to claim 13 wherein the primitive element matrix comprises first, second, third and fourth sub-matrixes that differ from each other; wherein each one of the first, second, third and fourth sub-matrixes comprises powers of a primitive element associated with at least one of the first and second versions.

15. A non-transitory computer readable medium that stores instructions that once executed by the computer causes the computer to perform the stages of:

receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the data unit;

selecting a first set of bits of the first version and a second set of bits of the second version;

encoding, in parallel, the first set of bits and the second set of bits;

wherein the encoding of the second set of bits is responsive to the second set of bits and a first redundancy result;

wherein the first redundancy result is calculated by applying an encoding process on a first payload that is associated with the first set of bits;

wherein the encoding of the first set of bits is responsive to the first set of bits and to a second redundancy result; and

wherein the second redundancy result is calculated by applying an encoding process on a second payload that is associated with the second set of bits.

16. The non-transitory computer readable medium according to claim 15 wherein the encoding, in parallel, of the first set of bits and the second set of bits generates a multi-dimensional codeword and comprises calculating redundancies that solving a linear equation system for computation of redundancies of the multi-dimensional codeword.

17. The non-transitory computer readable medium according to claim 15 , wherein the encoding, in parallel, of the first set of bits and the second set of bits comprises:

receiving or generating multiple first estimated results of encoding of the first set of bits and multiple second estimated results of the encoding of the second set of bits; and

finding, out of the multiple first and second estimated results, a pair of first and second estimated results that match outcomes of the encoding of the first set of bits and of the encoding of the second set of bits respectively.

18. The non-transitory computer readable medium according to claim 15 , wherein the encoding, in parallel, comprises receiving or calculating a syndrome vector and a primitive element matrix; and creating an equation system for a vector of redundancy bits that represents an output of the encoding of the first and second sets of bits.

19. The non-transitory computer readable medium according to claim 18 , wherein the primitive element matrix comprises first, second, third and fourth sub-matrixes that differ from each other; wherein each one of the first, second, third and fourth sub-matrixes comprises powers of a primitive element associated with at least one of the first and second versions.

20. A system comprising an encoder and a memory unit;

wherein the encoder is arranged to:

receive or generate a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the data unit;

select a first set of bits of the first version and a second set of bits of the second version; and

encode, in parallel, the first set of bits and the second set of bits;

wherein an encoding of the second set of bits is responsive to the second set of bits and a first redundancy result;

wherein the first redundancy result is calculated by applying an encoding process on a first payload that is associated with the first set of bits;

wherein the encoding of the first set of bits is responsive to the first set of bits and to a second redundancy result of the encoding of the second set of bits; and

wherein the second redundancy result is calculated by applying an encoding process on a second payload that is associated with the second set of bits.

Assignments (9)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
RELEASE OF SECURITY INTEREST Recorded Jan 11, 2017
From: KREOS CAPITAL IV (EXPERT FUND) LIMITED
To: DENSBITS TECHNOLOGIES LTD.
Reel/Frame 041339/0921 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2016
From: DENSBITS TECHNOLOGIES LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037622/0224 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2015
From: WEINGARTEN, HANAN; STEINER, AVI
To: DENSBITS TECHNOLOGIES LTD.
Reel/Frame 037078/0850 →
SECURITY INTEREST Recorded Mar 18, 2015
From: DENSBITS TECHNOLOGIES LTD.
To: KREOS CAPITAL IV (EXPERT FUND) LIMITED
Reel/Frame 035222/0547 →
Continuity (1)
Continuation 14323857 · Jul 3, 2014