IP Library Granted Patent US 9,444,135
Granted Patent B2
US 9,444,135 · App. 14/490,849 · Granted Sep 13, 2016

Integrated circuit package

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Quick Facts
Patent No.
US 9,444,135
App. No.
14/490,849
Granted
Sep 13, 2016
Kind
B2
Abstract

An integrated circuit package has a first side and an opposite second side. The integrated circuit package comprises: a stack of layers comprising at least a first and second electrically isolating layers, a dielectric material arranged on the stack of layers at the second side for encapsulating the integrated circuit package, a first integrated antenna structure for transmitting and/or receiving a first radio frequency signal, and a first array of electrically conductive vias extending through at least the first electrically isolating layer and the dielectric material. The first integrated antenna structure is arranged between the first and second electrically isolating layers and is surrounded by the electrically conductive vias which are electrically connected to respective first metal patches arranged on the dielectric material at the second side.

Claims (27)

1. An integrated circuit package having a first side and a second side opposite to the first side, the integrated circuit package comprising:

a stack of layers comprising at least a first electrically isolating layer and a second electrically isolating layer, the stack of layers being arranged at the first side of the integrated circuit package,

a dielectric material arranged on the stack of layers at the second side for encapsulating the integrated circuit package,

a first integrated antenna structure for transmitting and/or receiving a first radio frequency signal, the first integrated antenna structure being arranged between the first electrically isolating layer and the second electrically isolating layer,

a first array of electrically conductive vias extending through at least the first electrically isolating layer and the dielectric material,

the first integrated antenna structure being surrounded by the electrically conductive vias of the first array, the electrically conductive vias of the first array being electrically connected to respective first metal patches arranged on the dielectric material at the second side and separated from the integrated antenna structure by at least the dielectric material and the first electrically isolating layer.

2. An integrated circuit package according to claim 1 , the respective first metal patches being electrically connected to form a first metal path substantially surrounding the integrated antenna structure.

3. An integrated circuit package according to claim 2 , the first metal path being closed to form a first ring surrounding the first integrated antenna structure.

4. An integrated circuit package according to claim 2 , the first metal path being open in correspondence with an input of the first integrated antenna structure.

5. An integrated circuit package according to claim 1 , the electrically conductive vias being further electrically connected by a metal wall encapsulated by the dielectric material partially extending through the dielectric material and surrounding the integrated antenna structure.

6. An integrated circuit package according to claim 1 , the first integrated antenna structure being arranged for partly overlapping an electrically conductive layer, the electrically conductive layer being separated from the first integrated antenna structure by at least the second electrically isolating layer, the electrically conductive layer being arranged to reflect the radio frequency signal received by the electrically conductive layer through at least the second electrically isolating layer to the second side.

7. An integrated circuit package according to claim 6 , the stack of layers further comprising one or more electrically isolating layers for separating the first integrated antenna structure from the electrically conductive layer.

8. An integrated circuit package according to claim 6 , the electrical conductive layer and/or the electrically conductive vias of the first array being electrically connected to a reference potential.

9. An integrated circuit package according to claim 1 , the integrated antenna structure being electrically coupled to an integrated circuit die via one or more electrically conductive vias extending through at least the first electrically isolating layer, the integrated circuit die being arranged to generate the radio frequency signal for transmission via the integrated antenna structure and/or to receive the radio frequency signal as received via the integrated antenna structure.

10. An integrated circuit package according to claim 9 , the integrated circuit die being arranged inside the integrated circuit package and having a surface in direct contact with a surface of stack opposite to the second side.

11. An integrated circuit package assembly according to claim 9 , the integrated circuit die comprising a circuit of the group of circuits consisting of: a transmitter, a receiver, and a transceiver, the circuit being electrically coupled to the first integrated antenna structure.

12. An integrated circuit package according to claim 1 , further comprising:

a second integrated antenna structure for transmitting a second radio frequency signal, the second integrated antenna structure being arranged between the first electrically isolating layer and the second electrically isolating layer, and

a second array of electrically conductive vias extending through at least the first electrically isolating layer and the dielectric material,

the second integrated antenna structure being surrounded by the electrically conductive vias of the second array, the electrically conductive vias of the second array being electrically connected to respective second metal patches arranged on the dielectric material at the second side and separated from the second integrated antenna structure by at least the dielectric material and the first electrically isolating layer.

13. An integrated circuit package according to claim 12 , the respective second metal patches being electrically connected to form a second metal path.

14. An integrated circuit package according to claim 13 , the second metal path being closed to form a second ring surrounding the second integrated antenna structure.

15. An integrated circuit package according to claim 12 , the second electrically conductive vias of the second array being electrically connected by a second metal wall encapsulated by the dielectric material partially extending through the dielectric material and surrounding the second integrated antenna structure.

16. An integrated circuit package according to claim 12 , the second integrated antenna structure being electrically coupled to an integrated circuit die via second one or more electrically conductive vias through at least the first electrically isolating layer, the integrated circuit die being arranged to transmit the second radio frequency signal via the second integrated antenna structure and/or to receive the second radio frequency signal via the second integrated antenna structure.

17. An integrated circuit package assembly comprising the integrated circuit package according to claim 1 , the integrated circuit package assembly further comprising a printed circuit board for mounting the integrated circuit package on the printed circuit board at the first side.

18. An integrated circuit package assembly according to claim 17 , the printed circuit board comprising the electrically conductive layer.

19. An integrated circuit package assembly as claimed in claim 17 , the integrated circuit package assembly being used as a radar sensor for detecting targets in a field of view and arranged for transmitting and/or receiving the first radio frequency signal through a first predetermined frequency channel.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →