Interconnect structure

1. A microelectronic assembly comprising:

a first surface;

a first thin conductive element exposed on the first surface and having a first face consisting of first and second regions;

a first conductive projection having a base connected to and covering the first region of the first face and extending to an end remote therefrom, an edge surface extending between the base and the end, and a first barrier formed along a portion thereof, the first barrier having a first edge remote from the first thin conductive element;

a second surface having a second face;

a second thin conductive element on the second surface,

a second conductive projection having a base overlying the second surface, the second conductive projection extending away from the second thin conductive element to an end remote therefrom and having an edge surface extending between the base of the second conductive projection and the end of the second conductive projection, wherein the second conductive projection includes a second barrier layer formed along the edge surface of the second conductive projection adjacent the base, the second barrier having a second edge remote from the second thin conductive element; and

a first fusible metal mass connecting the first conductive projection to the second conductive projection such that the first face is oriented toward the second surface, wherein the first fusible metal mass extends along the edge surface of the first conductive projection to a location toward the first edge of the first barrier, the first barrier being disposed between the first thin conductive element and the first fusible metal mass, wherein the first fusible metal mass extends along the edge surfaces of the first and second conductive projections from the edge of the first barrier to the edge of the second barrier.

2. The microelectronic assembly of claim 1 , wherein the barrier is a surface-treatment layer formed on the first conductive projection.

3. The microelectronic assembly of claim 1 , wherein the surface-treatment layer is formed by oxidation.

4. The microelectronic assembly of claim 1 , wherein the surface-treatment layer is a coating applied on a surface of the first conductive projection.

5. The microelectronic assembly of claim 1 , wherein a layer of dielectric material covers the second region of the first thin conductive element.

6. The microelectronic assembly of claim 1 , wherein portions of the first fusible metal mass extend along the edges of the first and second conductive projections.

7. The microelectronic assembly of claim 1 , wherein the second surface is a substrate.

8. The microelectronic assembly of claim 1 , wherein the second barrier is a dielectric layer.

9. The microelectronic assembly of claim 1 , wherein the second conductive projection is one of a pillar or a pin.

10. The microelectronic assembly of claim 1 , wherein the first conductive projection and the second conductive projection are comprised of copper, and the first fusible metal mass is comprised of solder.

11. A microelectronic assembly, comprising:

a first subassembly including:

a first substrate having a first surface;

a plurality of first conductive pads, each having a first face exposed on the first surface;

a plurality of first projections, each defining a base having a periphery and connected to a respective one of the first conductive pads, the first projections extending away from the respective first conductive pads toward respective ends of the first projections, wherein exposed portions of the first faces of the conductive pads are defined outside of peripheries of the bases of the first projections; and

a first dielectric material layer overlying the exposed portions of the faces of the first conductive pads, and defining a plurality of openings through which respective ones of the first projections pass, the first dielectric material layer contacting at least the peripheries of the first projections and spaced away from the ends of the first projections so as to definine a first outer surface;

a second subassembly including:

a second substrate having a second face;

a plurality of second conductive pads exposed on the second face; and

a plurality of second projections, each of the plurality of second projections having a base connected to a respective one of the second conductive pads and extending away from the respective second conductive pads toward respective ends of the plurality of second projections, and

a second dielectric material layer overlying exposed portions of the second conductive pads and having a first outer surface, the first outer surfaces of the second projections being spaced away from the ends of the second projections, the exposed portions of the second conductive pads being defined outside of peripheries of the bases of the second projections; and

a plurality of fusible metal masses respectively joining the plurality of first projections to respective ones of the plurality of second projections such that the second face of the second substrate is oriented toward the first surface of the first substrate, wherein the fusible metal masses cover at least portions of the first projections extending to the first outer surface of the first dielectric material layer and at least portions of the second projections extending to the first outer surface of the second dielectric material layer.

12. The microelectronic assembly of claim 11 , wherein the plurality of first conductive pads are comprised of copper and the fusible metal masses are comprised of copper.

13. The microelectronic assembly of claim 11 , wherein the plurality of second conductive projections are one of a pillar or a pin.

14. The microelectronic assembly of claim 11 , wherein the assembly further comprises a microelectronic element positioned between the first and second substrates, the microelectronic assembly having a plurality of third projections extending away from the microelectronic element, the third projections electrically connected with the first and second projections.

15. The microelectronic assembly of claim 11 , wherein the assembly further comprises a microelectronic element overlying the first and second substrates, the microelectronic element further including a plurality of third projections extending away therefrom and electrically connected with the first and second projections.

16. A microelectronic assembly comprising:

a first substrate having a first surface;

a first thin conductive element exposed on the first surface and having a first face;

a first conductive projection having a base connected to the first face and extending to an end remote from the first face, a side wall being defined between the base and the end;

a dielectric material layer having a second surface and a third surface remote from the second surface, the second surface extending along the first surface of the first substrate, the dielectric material layer having a first opening defining a periphery formed therein;

a metal plating layer having a first portion extending along the end and at least a portion of the side wall of the first conductive projection and a second portion extending outwardly along a portion of the dielectric material layer and away from the first conductive projection; and

a first solder mass formed over at least the first portion of the metal plating layer and extending toward the third surface.

17. The microelectronic assembly of claim 16 , wherein the first conductive projection is one of a pillar or a pin.