Fast secure erase in a flash system

1. A method for erasing information stored in a flash memory device, comprising:

receiving a fast erase signal to erase one or more groups of flash memory cells in the flash memory device;

switching, by a flash memory controller, operating parameters of the flash memory device from first parameters corresponding to a first erase mode to second parameters corresponding to a second erase mode based on receiving the fast erase signal, the first erase mode for erasing the one or more groups of flash memory cells using a plurality of erase pulses and the second erase mode for erasing the one or more groups of flash memory cells using a single erase pulse, wherein an erase operation in the first erase mode is an incremental stepping pulse erase operation and the flash memory device is configured to perform the erase operation in the first erase mode by default; and

instructing the flash memory device to perform an erase operation to erase the one or more groups of flash memory cells according to the second parameters.

2. The method of claim 1 , further comprising:

verifying that the erase operation was completed using the single erase pulse.

3. The method of claim 2 , further comprising:

writing random data to the one or more groups of flash memory cells after the erase operation is completed.

4. The method of claim 1 , wherein switching the operating parameters comprises:

obtaining a pulse voltage for the erase operation based on a current number of cycles for the one or more groups of flash memory cells; and

instructing the flash memory device to perform the erase operation using the obtained pulse voltage.

5. The method of claim 4 , wherein obtaining the pulse voltage comprises:

indexing a lookup table by the current number of cycles to obtain the pulse voltage from the lookup table.

6. The method of claim 1 , wherein each group of flash memory cells is arranged and addressed by the flash memory controller as a memory block, the method further comprising:

in response to receiving the fast erase signal, instructing the flash memory device to perform the erase operation, according to the second parameters, for all memory blocks in the flash memory device.

7. The method of claim 6 , further comprising:

in response to receiving the fast erase signal, switching operating parameters of a plurality of flash memory devices from the first parameters to the second parameters, and instructing each of the plurality of flash memory devices to perform erase operations in parallel, according to the second parameters, to erase all memory blocks in each respective flash memory device.

8. A data storage system, comprising:

a plurality of flash memory devices, each flash memory device comprising a plurality of memory blocks; and

a controller coupled to the plurality of flash memory devices, wherein the controller is configured to:

erase memory cells of one or more of the flash memory devices using a first erase mode or a second erase mode, the first erase mode for erasing the memory cells using a plurality of erase pulses and the second erase mode for erasing the memory cells using a single erase pulse;

receive a fast erase signal for erasing one or more respective memory blocks of one or more of the plurality of flash memory devices according to the second erase mode;

switch operating parameters of the one or more flash memory devices from first parameters corresponding to the first erase mode to second parameters corresponding to the second erase mode based on receiving the fast erase signal, wherein an erase operation in the first erase mode is an incremental stepping pulse erase operation and each of the one or more flash memory devices is configured to perform the erase operation in the first erase mode by default; and

instruct the one or more flash memory devices to perform an erase operation to erase the one or more respective memory blocks according to the second parameters.

9. The data storage system of claim 8 , wherein the controller is further configured to:

verify the erase operation was completed using the single erase pulse.

10. The data storage system of claim 8 , wherein switching the operating parameters comprises:

obtaining an erase pulse voltage for the erase operation based on a current number of cycles for the one or more respective memory blocks; and

instructing the one or more of the flash memory devices to perform the erase operation using the obtained pulse voltage.

11. The data storage system of claim 10 , wherein obtaining the erase pulse voltage comprises:

indexing a lookup table by the current number of cycles to obtain the erase pulse voltage from the lookup table.

12. The data storage system of claim 8 , wherein the controller is further configured to:

write random data to the one or more respective memory blocks after the erase operation is completed.

13. The data storage system of claim 8 , wherein the controller is further configured to:

in response to receiving the fast erase signal, instruct each of the one or more flash memory devices to perform the erase operation, according to the second parameters, for all memory blocks in the flash memory device.

14. The data storage system of claim 13 , wherein the controller is further configured to:

in response to receiving the fast erase signal, switch operating parameters of the plurality of flash memory devices from the first parameters to the second parameters, and instruct each of the plurality of flash memory devices to perform erase operations in parallel, according to the second parameters, to erase all memory blocks in each respective flash memory device.

15. A computer program product tangibly embodied in a data storage device and comprising instructions that, when executed by the data storage device, cause the data storage device to:

receive a fast erase signal to erase one or more blocks of flash memory cells in a flash memory;

switch, in response to the fast erase signal, operating parameters of the flash memory from first parameters corresponding to a first erase mode to second parameters corresponding to a second erase mode, the first erase mode for erasing the one or more blocks of flash memory cells using a plurality of erase pulses and the second erase mode for erasing the one or more blocks of flash memory using a single erase pulse, wherein an erase operation in the first erase mode is an incremental stepping pulse erase operation and the flash memory device is configured to perform the erase operation in the first erase mode by default;

instruct the flash memory to perform an erase operation to erase the one or more blocks of flash memory cells according to the second parameters.

16. The computer program product of claim 15 , wherein switching the operating parameters comprises:

indexing a lookup table by a current number of cycles for the one or more blocks; and

obtaining a pulse voltage for the erase operation from the lookup table based on the current number of cycles.

17. The computer program product of claim 16 , wherein the instructions, when executed by the data storage device, further cause the data storage device to:

instruct the flash memory to perform the erase operation using the obtained pulse voltage; and

verify that the erase operation was completed using the single erase pulse at the obtained pulse voltage.

18. The computer program product of claim 15 , wherein the instructions, when executed by the data storage device, further cause the data storage device to:

write random data to the one or more blocks of memory cells after the erase operation is completed.

19. The computer program product of claim 15 , wherein the instructions, when executed by the data storage device, further cause the data storage device to:

in response to receiving the fast erase signal, instruct the flash memory to perform the erase operation, according to the second parameters, for all memory blocks in the flash memory.

20. The computer program product of claim 19 , wherein the instructions, when executed by the data storage device, further cause the data storage device to:

in response to receiving the fast erase signal, switching operating parameters of multiple flash memory devices from the first parameters to the second parameters, and instruct the multiple flash memory to perform erase operations in parallel, according to the second parameters, for all memory blocks in each respective flash memory.