Semiconductor device performing refresh operation
Disclosed herein is a device that includes a first semiconductor chip. The first semiconductor chip includes a first data storage area storing data, a first refresh circuit repeating a first refresh operation on the first data storage area to make the first data storage area retain the data, a first terminal supplied with a first control signal from outside of the first semiconductor chip, and a first control circuit coupled between the first terminal and the first refresh circuit to control a repetition cycle of the first refresh operation in response to the first control signal.
1. A device comprising:
a first semiconductor chip;
a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip including a first plurality of through electrodes penetrating therethrough; and
a refresh control unit which controls a cycle of a refresh for the second semiconductor chip in response to a first temperature signal received via at least one through electrode of the first plurality of through electrodes;
wherein the first semiconductor chip includes a first temperature sensor outputting the first temperature signal, and the first temperature signal takes a first value when a temperature of the first semiconductor chip is equal to or higher than a first temperature and a second value when the temperature of the first semiconductor chip is lower than the first temperature, and wherein the refresh control unit controls the cycle to a first cycle when the first temperature signal takes the first value and to a second cycle that is greater than the first cycle when the first temperature signal takes the second value.
2. The device as claimed in claim 1 , wherein a refresh control unit is included in the second semiconductor chip.
3. The device as claimed in claim 1 , wherein
the second semiconductor chip has a second temperature sensor outputting a second temperature signal,
the second temperature signal taking a third value when a temperature of the second semiconductor chip is equal to or higher than a second temperature and a fourth value when the temperature of the second semiconductor chip is lower than the second temperature, and
the refresh control unit controls the cycle to the first cycle in response to at least one of the first temperature signal taking the first value and the second temperature signal taking the third value and to the second cycle in response to at least one of the first temperature signal taking the second value and the second temperature signal taking the fourth value.
4. The device as claimed in claim 1 , wherein
the second semiconductor chip has a second temperature sensor outputting a second temperature signal, and
the refresh control unit further controls the cycle in response to the second temperature signal.
5. The device as claimed in claim 4 , further comprising a third semiconductor chip that includes the refresh control unit.
6. The device as claimed in claim 1 , further comprising a package substrate on which the first and second semiconductor chips are mounted,
wherein the first and second semiconductor chips and the package substrate are encapsulated continuously by a resin.
7. The device as claimed in claim 1 , wherein each of the first plurality of through electrodes includes at least 512 through electrodes.
8. The device as claimed in claim 1 , wherein the first semiconductor chip includes a second plurality of through electrodes and the first temperature signal is received via at least one through electrode of the second plurality of through electrodes.
9. The device as claimed in claim 1 , wherein the first semiconductor chip is a system-on-chip.
10. The device as claimed in claim 1 , wherein the first semiconductor chip is a controller chip.