Magnetic recording disk drive with write current overshoot amplitude (OSA) responsive to data transitions
View Patent ↗A disk drive dynamic wave shaper (DWS) write driver includes a write current generator that produces a baseline output current for the write current pulses and an overshoot current generator that produces an overshoot current with different values. The overshoot current is added to the baseline current, with the value of the overshoot current amplitude (OSA) being selected in response to the frequency of transitions in the write data signal. The write driver includes logic circuitry that detects the pattern of transitions. Transitions that are immediately followed by a transition will receive a larger-than-nominal OSA1, transitions that are not immediately followed by a transition and that are not preceded by a long sequence of non-transitions will receive a nominal OSA2, and transitions after longer sequences of non-transitions will receive a smaller-than-nominal OSA3.
1. A disk drive preamplifier comprising:
a write driver that receives a clock signal and a digital write data input signal and generates analog write current pulses corresponding to transitions in the digital write data input signal, the write driver including:
a write current generator that produces a baseline output current for the write current pulses; and
an overshoot current generator that produces an overshoot current that is added to the baseline current, the overshoot current generator including logic circuitry that generates, from the digital write data input signal, a first overshoot signal in response to a transition with no immediately successive transition, a second overshoot signal greater than said first overshoot signal in response to consecutive transitions, and a third overshoot signal less than said first overshoot signal in response to a predetermined number of non-transitions.
2. The preamplifier of claim 1 wherein the logic circuitry includes a one-clock-cycle delay register having a value D1 and a two-clock-cycle delay register having a value D2 for the digital write data input signal.
3. The preamplifier of claim 2 wherein the logic circuitry receives, from the digital write data input signal, an input data bit having a value D and detects consecutive transitions according to the logic expression (D XOR D2)′.
4. The preamplifier of claim 1 wherein the logic circuitry includes a clock-cycle counter initiated by a transition and a clock-count register having a predetermined count value, and wherein the logic circuitry generates said third overshoot signal when the clock-cycle counter equals the clock-count in said register.
5. The preamplifier of claim 4 wherein the logic circuitry includes a one-clock-cycle delay register having a value D1 and a two-clock-cycle delay register having a value D2 for the digital write data input signal, and wherein the clock-cycle counter is initiated from the logic expression (D1 XOR D2).
6. A magnetic recording disk drive comprising:
system electronics that supplies a clock signal and a digital write data input signal;
a write driver that receives a clock signal and the digital write data input signal and generates analog write current pulses corresponding to transitions in the digital write data input signal, the write driver including:
a write current generator that produces a baseline output current for the write current pulses; and
an overshoot current generator that produces an overshoot current that is added to the baseline current, the overshoot current generator including logic circuitry that generates, from the digital write data input signal, a first overshoot signal in response to a transition with no immediately successive transition, a second overshoot signal greater than said first overshoot signal in response to consecutive transitions, and a third overshoot signal less than said first overshoot signal in response to a predetermined number of consecutive non-transitions; and
a write head including an inductive coil that receives the write current pulses from the write driver.
7. The disk drive of claim 6 wherein the logic circuitry includes a one-clock-cycle delay register having a value D1 and a two-clock-cycle delay register having a value D2 for the digital write data input signal.
8. The disk drive of claim 7 wherein the logic circuitry receives, from the digital write data input signal, an input data bit having a value D and detects consecutive transitions according to the logic expression (D XOR D2)′.
9. The disk drive of claim 7 wherein the logic circuitry includes a clock-cycle counter initiated by a transition and a clock-count register having a predetermined count value, wherein the logic circuitry generates said third overshoot signal when the clock-cycle counter equals the clock-count in said register, and wherein the clock-cycle counter is initiated from the logic expression (D1 XOR D2).
10. The disk drive of claim 9 wherein the system electronics supplies serial data to the write driver, and wherein said predetermined count value in said clock-count register is programmed into said register from the system electronics.
11. A disk drive preamplifier comprising:
a write driver that receives a clock signal and a digital write data input signal and generates analog write current pulses corresponding to transitions in the digital write data input signal, the write driver including:
a write current generator that produces a baseline output current for the write current pulses; and
an overshoot current generator that produces an overshoot current that is added to the baseline current, the overshoot current generator including logic circuitry that generates, from the digital write data input signal, a first overshoot signal in response to a transition with no immediately successive transition, and a second overshoot signal greater than said first overshoot signal in response to consecutive transitions; wherein the logic circuitry includes a one-clock-cycle delay register having a value D1 and a two-clock-cycle delay register having a value D2 for the digital write data input signal.
12. The preamplifier of claim 11 wherein the logic circuitry receives, from the digital write data input signal, an input data bit having a value D and detects consecutive transitions according to the logic expression (D XOR D2)′.
13. The preamplifier of claim 11 wherein the logic circuitry generates a third overshoot signal less than said first overshoot signal in response to a predetermined number of non-transitions.
14. The preamplifier of claim 13 wherein the logic circuitry includes a clock-cycle counter initiated by a transition and a clock-count register having a predetermined count value, and wherein the logic circuitry generates said third overshoot signal when the clock-cycle counter equals the clock-count in said register.
15. The preamplifier of claim 14 wherein the logic circuitry includes a one-clock-cycle delay register having a value D1 and a two-clock-cycle delay register having a value D2 for the digital write data input signal, and wherein the clock-cycle counter is initiated from the logic expression (D1 XOR D2).