IP Library Granted Patent US 9,059,033
Granted Patent B2
US 9,059,033 · App. 14/532,311 · Granted Jun 16, 2015

Semiconductor device with pads of enhanced moisture blocking ability

Inventors: Kaoru Saigoh (Kawasaki, JP); Kouichi Nagai (Kawasaki, JP)
Assignee: FUJITSU SEMICONDUCTOR LIMITED
H01L27/11507H01L23/564H01L24/13H01L24/05H01L2224/13023H01L2224/13014H01L2224/13144H01L2224/0401H01L2224/05083H01L2224/05164H01L2924/01013H01L2924/01022H01L2924/01007H01L2224/05666
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Quick Facts
Patent No.
US 9,059,033
App. No.
14/532,311
Granted
Jun 16, 2015
Kind
B2
Abstract

A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

Claims (19)

1. A semiconductor device comprising:

a semiconductor substrate;

a circuit portion including a plurality of semiconductor elements formed on said semiconductor substrate;

lamination of insulator covering said circuit portion, formed on said semiconductor substrate and including a passivation film as an uppermost layer having an opening;

a ferro-electric capacitor formed in said lamination of insulator;

a wiring structure formed in said lamination of insulator and connected to said semiconductor elements and said ferro-electric capacitor;

a pad electrode structure connected to said wiring structure, formed in said lamination of insulator and exposed in the opening of said passivation film;

a conductive pad protection film including a Pd film, covering said pad electrode structure via the opening of said passivation film, and extending on said passivation film; and

a conductive capacitor protection film made of a same film as said conductive pad protection film and extending on said passivation film in an area including an area above said ferro-electric capacitor in a state electrically separated from said conductive pad protection film.

2. The semiconductor device according to claim 1 , wherein said conductive capacitor protection film is electrically separated from said conductive pad protection film by a slit.

3. The semiconductor device according to claim 1 , wherein said pad electrode structure has an uppermost surface of aluminum or aluminum alloy, and said uppermost surface has a flaw formed by needle abutment.

4. The semiconductor device according to claim 3 , wherein said conductive pad protection film covers a surface of said flaw.

5. The semiconductor device according to claim 4 , wherein said conductive pad protection film includes a Ti film contacting said uppermost surface of aluminum or aluminum alloy.

6. The semiconductor device according to claim 5 , wherein said conductive pad protection film includes a TiN film or a Ti—Al—N film between said Pd film and said Ti film.

7. The semiconductor device according to claim 1 , further comprising a plated bump formed on said conductive pad protection film.

8. The semiconductor device according to claim 7 , wherein said plated bump is made of gold.

9. The semiconductor device according to claim 7 , wherein said pad electrode structure has an uppermost surface of aluminum or aluminum alloy, and said uppermost surface has a flaw formed by needle abutment.

10. The semiconductor device according to claim 7 , wherein said conducive pad protection film covers the surface of said flaw.

11. The semiconductor device according to claim 10 , wherein said conductive pad protection film includes a Ti film contacting said uppermost surface of aluminum or aluminum alloy.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED
Reel/Frame 053195/0249 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2014
From: SAIGOH, KAORU; NAGAI, KOUICHI
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 034098/0521 →
Continuity (4)
Division 13293628 · Nov 10, 2011
Division 12163418 · Jun 27, 2008
Continuation PCTJP2005023964 · Dec 27, 2005
Related Publication 20150054129A1 · Feb 26, 2015