IP Library Granted Patent US 9,313,053
Granted Patent B2
US 9,313,053 · App. 14/543,709 · Granted Apr 12, 2016

Filter circuitry

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Quick Facts
Patent No.
US 9,313,053
App. No.
14/543,709
Granted
Apr 12, 2016
Kind
B2
Abstract

Embodiments provide methods, devices, circuitry and systems for supporting or implementing functionality to provide a filtering circuit, and for providing a transmitter, receiver or transceiver system incorporating the same. One embodiment provides a circuit for filtering signals. The circuit comprises a first connection configured to be connected to a signal line carrying varying signal voltage and a second connection. The circuit also comprises a first circuit portion comprising a parallel resonant circuit having a variable capacitance connected in parallel with a first inductor; and a second circuit portion comprising a second inductor. The first circuit portion and the second circuit portion are connected in series between the first connection and the second connection.

Claims (85)

1. A circuit configured to filter signals, the circuit comprising:

a first connection configured to be connected to a signal line carrying varying signal voltage;

a second connection;

a first circuit portion comprising a parallel resonant circuit, the parallel resonant circuit comprising a variable capacitance connected in parallel with a first inductor; and

a second circuit portion comprising a second inductor, wherein

the first circuit portion and the second circuit portion are connected in series between the first connection and the second connection,

a first inductance of the first inductor is greater than a second inductance of the second inductor, and

the first inductance and the second inductance are selected such that a ratio of the first inductance to the second inductance n satisfies n=(H 2 −1) −1 , where H is an integer and n is a fraction.

2. The circuit of claim 1 , wherein

H is equal to 2 and n is equal to 1/3.

3. The circuit of claim 1 , wherein

H is equal to 3 and n is equal to 1/8.

4. The circuit of claim 1 , further comprising:

a third circuit portion comprising a third inductor, wherein

the first circuit portion, the second circuit portion and the third circuit portion are connected in series between the first connection and the second connection,

the first circuit portion is connected between the second circuit portion and the third circuit portion,

the second connection is connected to a second signal line, and

the first signal line and the second signal line carry balanced signals.

5. The circuit of claim 4 , wherein

the second inductance of the second inductor and a third inductance of the third inductor are the same.

6. The circuit of claim 4 , wherein

the first circuit portion comprises a fourth inductor, and the first inductor and the fourth inductor are connected in series, the first inductor and the fourth inductor together being connected in parallel with the variable capacitance, and

the circuit comprises a third connection connected between the first inductor and the fourth inductor, the third connection being configured to be connected to a reference line held at a reference voltage.

7. The circuit of claim 6 , wherein

the first inductance of the first inductor and a fourth inductance of the fourth inductor are the same.

8. The circuit of claim 6 , wherein

the first inductor and the fourth inductor are co-centered and counter-wound.

9. The circuit of claim 6 , wherein

the second inductor and the third inductor are co-centered and counter-wound.

10. The circuit of claim 6 , wherein

each of the first inductor, the second inductor, the third inductor and the fourth inductor is co-centered.

11. The circuit of claim 4 , further comprising:

amplifying circuitry, wherein

the first connection is connected to a first output of the amplifying circuitry and the second connection is connected to a second output of the amplifying circuitry.

12. The circuit of claim 11 , further comprising:

a first resistor connected between a first input of the amplifying circuitry and the connection between the first circuit portion and the second circuit portion; and

a second resistor connected between a second input of the amplifying circuitry and the connection between the first circuit portion and the third circuit portion.

13. The circuit of claim 4 , further comprising:

mixing circuitry, wherein

the first connection is connected to a first output of the mixing circuitry and the second connection is connected to a second output of the mixing circuitry.

14. The circuit of claim 1 , wherein

the second connection is configured to be connected to a reference line held at a reference voltage.

15. The circuit of claim 14 , further comprising:

amplifying circuitry, wherein

the first connection is connected to an output of the amplifying circuitry, such that the first circuit portion and the second circuit portion are connected in series between the output of the amplifying circuitry and the second connection.

16. The circuit of claim 14 , further comprising:

mixing circuitry, wherein

the first connection is connected to an output of the mixing circuitry, such that the first circuit portion and the second circuit portion are connected in series between an output of the mixing circuitry and the second connection.

17. The circuit of claim 1 , wherein

the variable capacitance comprises a variable capacitor, a bank of independently selectable capacitors and/or a varactor.

18. Circuitry for use in a direct conversion transmitting chain, the circuitry comprising:

mixing circuitry configured to upconvert base band signals to provide radio frequency signals;

amplifying circuitry configured to amplify radio frequency signals; and

filtering circuitry connected between the mixing circuitry and the amplifying circuitry, the filtering circuitry comprising

a first connection configured to be connected to a signal line carrying varying signal voltage;

a second connection;

a first circuit portion comprising a parallel resonant circuit, the parallel resonant circuit comprising a variable capacitance connected in parallel with a first inductor; and

a second circuit portion comprising a second inductor, wherein

the first circuit portion and the second circuit portion are connected in series between the first connection and the second connection, and

a ratio n of a first inductance of the first inductor to a second inductance of the second inductor satisfies n=(H 2 −1) −1 , where H is an integer and n is a fraction.

19. The circuitry according to claim 18 , wherein

the mixing circuitry is connected to a local oscillator producing a square wave, and

the first inductance is eight times that of the second inductance.

20. Circuitry comprising:

a first connection configured to be connected to a signal line carrying varying signal voltage;

a second connection;

a first circuit portion comprising a parallel resonant circuit, the parallel resonant circuit comprising a variable capacitance connected in parallel with a first inductor; and

a second circuit portion comprising a second inductor, wherein

the first circuit portion and the second circuit portion are connected in series between the first connection and the second connection, and

a ratio n of a first inductance of the first inductor to a second inductance of the second inductor satisfies n=(H 2 −1) −1 , where H is an integer and n is a fraction.

21. The circuitry of claim 20 , further comprising:

amplifying circuitry, wherein

the first connection is connected to a first output of the amplifying circuitry and the second connection is connected to a second output of the amplifying circuitry.

22. The circuitry of claim 20 , further comprising:

a third circuit portion comprising a third inductor, wherein

the first circuit portion, the second circuit portion and the third circuit portion are connected in series between the first connection and the second connection,

the first circuit portion is connected between the second circuit portion and the third circuit portion,

the second connection is connected to a second signal line, and

the first signal line and the second signal line carry balanced signals.

23. The circuitry of claim 22 , further comprising:

amplifying circuitry, wherein

the first connection is connected to a first output of the amplifying circuitry and the second connection is connected to a second output of the amplifying circuitry,

a first resistor is connected between a first input of the amplifying circuitry and the connection between the first circuit portion and the second circuit portion, and

a second resistor is connected between a second input of the amplifying circuitry and the connection between the first circuit portion and the third circuit portion.

24. The circuitry of claim 20 , wherein H is equal to 2 or 3 and n is equal to 1/3 or 1/8.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →