Semiconductor integrated circuit device
View Patent ↗In IC chips for display device driving, an operational amplifier is widely used in input and output circuits, and a capacitor in a medium withstanding voltage chip is used as a compensation capacitor. As for this product area, cost competitiveness is very important. Therefore, a MIS capacitor with good area efficiency is widely used. However, unlike a so-called varactor widely used in a VCO circuit, a characteristic of as small a voltage dependence of the capacitor as possible is used. Therefore, an additional process is added to reduce the voltage dependence of the capacitor, but there is a problem of an increase in process cost. A semiconductor substrate side capacitor electrode in a MIS capacitor within a first conduction type medium withstanding voltage chip used in an I/O circuit or the like on a semiconductor integrated circuit device is formed in a first conduction type low withstanding voltage well region.
1. A semiconductor integrated circuit device, comprising:
(a) a semiconductor substrate having a first main surface;
(b) a first N-type low withstanding voltage well region formed on the first main surface of the semiconductor substrate;
(c) a P-channel type low withstanding voltage MISFET formed in a surface region of the first N-type low withstanding voltage well region;
(d) a second N-type low withstanding voltage well region formed on the first main surface of the semiconductor substrate simultaneously with the first N-type low withstanding voltage well region;
(e) an N-type medium withstanding voltage MIS capacitor that is provided in a surface region of the second N-type low withstanding voltage well region, has a higher withstanding voltage than the P-channel type low withstanding voltage MISFET, and has the second N-type low withstanding voltage well region as one capacitor electrode;
(f) a first N-type medium withstanding voltage well region formed on the first main surface of the semiconductor substrate; and,
(g) a P-channel type medium withstanding voltage MISFET formed in a surface region of the first N-type medium withstanding voltage well region,
wherein a medium withstanding voltage capacitor insulating film of the N-type medium withstanding voltage MIS capacitor has an equal thickness with a medium withstanding voltage gate insulating film of the P-channel type medium withstanding voltage MISFET, and is thicker than a low withstanding voltage gate insulating film of the P-channel type low withstanding voltage MISFET.
2. The semiconductor integrated circuit device according to claim 1 ,
wherein the other capacitor electrode of the N-type medium withstanding voltage MIS capacitor is an N-type polysilicon electrode.
3. The semiconductor integrated circuit device according to claim 2 ,
wherein the semiconductor substrate is a P-type silicon single-crystal substrate.
4. The semiconductor integrated circuit device according to claim 3 , further comprising:
(h) a first P-type low withstanding voltage well region formed on the first main surface of the semiconductor substrate;
(i) an N-channel type low withstanding voltage MISFET formed in a surface region of the first P-type low withstanding voltage well region;
(j) a second P-type low withstanding voltage well region formed on the first main surface of the semiconductor substrate simultaneously with the first P-type low withstanding voltage well region; and
(k) a P-type medium withstanding voltage MIS capacitor that is provided in a surface region of the second P-type low withstanding voltage well region, has a higher withstanding voltage than the N-channel type low withstanding voltage MISFET, and has the second P-type low withstanding voltage well region as one capacitor electrode.
5. The semiconductor integrated circuit device according to claim 4 ,
wherein the semiconductor integrated circuit device is for display device driving.
6. The semiconductor integrated circuit device according to claim 4 ,
wherein the semiconductor integrated circuit device is for liquid crystal display device driving.
7. The semiconductor integrated circuit device according to claim 6 , further comprising:
(l) a first N-type high withstanding voltage well region that is formed on the first main surface of the semiconductor substrate so as to include the first P-type low withstanding voltage well region in a planer manner and is deeper than the first P-type low withstanding voltage well region; and
(m) a second N-type high withstanding voltage well region that is formed on the first main surface of the semiconductor substrate so as to include the second P-type low withstanding voltage well region in a planer manner, is deeper than the second P-type low withstanding voltage well region, and is formed simultaneously with the first N-type high withstanding voltage well region.
8. The semiconductor integrated circuit device according to claim 3 , further comprising:
(n) an N-type doped region for threshold voltage adjustment formed in a channel region of the first N-type low withstanding voltage well region; and
(o) a capacitor N-type doped region that is formed in a region near a surface of the second N-type low withstanding voltage well region, which is located opposite the other capacitor electrode, simultaneously with the N-type doped region for threshold voltage adjustment.
9. The semiconductor integrated circuit device according to claim 3 , further comprising:
(p) a third N-type high withstanding voltage well region that is formed on the first main surface of the semiconductor substrate simultaneously with the first N-type high withstanding voltage well region so as to be deeper than the second P-type low withstanding voltage well region;
(q) the second P-type low withstanding voltage well region formed on the first main surface of the semiconductor substrate so as to be included in the third N-type high withstanding voltage well region in a planar manner; and
(r) a P-type medium withstanding voltage MIS capacitor that is provided in a surface region of the second P-type low withstanding voltage well region, has a higher withstanding voltage than the P-channel type low withstanding voltage MISFET, and has the second P-type low withstanding voltage well region as one capacitor electrode,
wherein the first N-type medium withstanding voltage well region is formed on the first main surface of the semiconductor substrate so as to be included in the third N-type high withstanding voltage well region in a planar manner.
10. The semiconductor integrated circuit device according to claim 9 , further comprising:
(s) a first P-type medium withstanding voltage well region that is provided on the first main surface of the semiconductor substrate and is provided between the first N-type medium withstanding voltage well region and the second P-type low withstanding voltage well region so as to be in contact with the first N-type medium withstanding voltage well region and the second P-type low withstanding voltage well region.
11. A semiconductor integrated circuit device, comprising:
(a) a semiconductor substrate having a first main surface;
(b) a first P-type low withstanding voltage well region formed on the first main surface of the semiconductor substrate;
(c) an N-channel type low withstanding voltage MISFET formed in a surface region of the first P-type low withstanding voltage well region;
(d) a second P-type low withstanding voltage well region formed on the first main surface of the semiconductor substrate simultaneously with the first P-type low withstanding voltage well region;
(e) a P-type medium withstanding voltage MIS capacitor that is provided in a surface region of the second P-type low withstanding voltage well region, has a higher withstanding voltage than the N-channel type low withstanding voltage MISFET, and has the second P-type low withstanding voltage well region as one capacitor electrode,
(f) a first P-type medium withstanding voltage well region formed on the first main surface of the semiconductor substrate; and,
(g) a N-channel type medium withstanding voltage MISFET formed in a surface region of the first P-type medium withstanding voltage well region,
wherein a medium withstanding voltage capacitor insulating film of the P-type medium withstanding voltage MIS capacitor has an equal thickness with a medium withstanding voltage gate insulating film of the N-channel type medium withstanding voltage MISFET, and is thicker than a low withstanding voltage gate insulating film of the N-channel type low withstanding voltage MISFET.
12. The semiconductor integrated circuit device according to claim 11 ,
wherein the other capacitor electrode of the P-type medium withstanding voltage MIS capacitor is a P-type polysilicon electrode.
13. The semiconductor integrated circuit device according to claim 12 ,
wherein the semiconductor substrate is a P-type silicon single-crystal substrate.
14. The semiconductor integrated circuit device according to claim 13 , further comprising:
(h) a first N-type low withstanding voltage well region formed on the first main surface of the semiconductor substrate;
(i) a P-channel type low withstanding voltage MISFET formed in a surface region of the first N-type low withstanding voltage well region;
(j) a second N-type low withstanding voltage well region formed on the first main surface of the semiconductor substrate simultaneously with the first N-type low withstanding voltage well region; and
(k) an N-type medium withstanding voltage MIS capacitor that is provided in a surface region of the second N-type low withstanding voltage well region, has a higher withstanding voltage than the P-channel type low withstanding voltage MISFET, and has the second N-type low withstanding voltage well region as one capacitor electrode.
15. The semiconductor integrated circuit device according to claim 14 ,
wherein the semiconductor integrated circuit device is for display device driving.
16. The semiconductor integrated circuit device according to claim 14 ,
wherein the semiconductor integrated circuit device is for liquid crystal display device driving.
17. The semiconductor integrated circuit device according to claim 16 , further comprising:
(l) a first N-type high withstanding voltage well region that is formed on the first main surface of the semiconductor substrate so as to include the first P-type low withstanding voltage well region in a planer manner and is deeper than the first P-type low withstanding voltage well region; and
(m) a second N-type high withstanding voltage well region that is formed on the first main surface of the semiconductor substrate so as to include the second P-type low withstanding voltage well region in a planer manner, is deeper than the second P-type low withstanding voltage well region, and is formed simultaneously with the first N-type high withstanding voltage well region.
18. The semiconductor integrated circuit device according to claim 13 , further comprising:
(n) a P-type doped region for threshold voltage adjustment formed in a channel region of the first P-type low withstanding voltage well region; and
(o) a capacitor P-type doped region that is formed in a region near a surface of the second P-type low withstanding voltage well region, which is located opposite the other capacitor electrode, simultaneously with the P-type doped region for threshold voltage adjustment.
19. The semiconductor integrated circuit device according to claim 13 , further comprising:
(p) a third N-type high withstanding voltage well region that is formed on the first main surface of the semiconductor substrate simultaneously with the first N-type high withstanding voltage well region so as to be deeper than the second P-type low withstanding voltage well region;
(q) the second P-type low withstanding voltage well region formed on the first main surface of the semiconductor substrate so as to be included in the third N-type high withstanding voltage well region in a planar manner; and
(r) a P-type medium withstanding voltage MIS capacitor that is provided in a surface region of the second P-type low withstanding voltage well region, has a higher withstanding voltage than the P-channel type low withstanding voltage MISFET, and has the second P-type low withstanding voltage well region as one capacitor electrode,
wherein the first P-type medium withstanding voltage well region is formed on the first main surface of the semiconductor substrate so as to be included in the third P-type high withstanding voltage well region in a planar manner.
20. The semiconductor integrated circuit device according to claim 19 , further comprising:
(s) a first P-type medium withstanding voltage well region that is provided on the first main surface of the semiconductor substrate and is provided between the first N-type medium withstanding voltage well region and the second P-type low withstanding voltage well region so as to be in contact with the first N-type medium withstanding voltage well region and the second P-type low withstanding voltage well region.