Manufacturing method for semiconductor device

1. A manufacturing method for a semiconductor device including a non-volatile memory FET and a MOSFET, comprising:

(e) forming a first gate electrode film on the entire surface of a semiconductor substrate;

(i) opening a region having the non-volatile memory FET formed therein and exposing a semiconductor surface of the semiconductor substrate, after the step (e);

(m) forming a charge storage three-layer film by sequentially depositing a first potential barrier film, a charge storage film, and a second potential barrier film, after the step (i);

(n) forming a second gate electrode film on the charge storage three-layer film, after the step (m);

(o) patterning a gate electrode of the non-volatile memory FET after the step (n);

(p) forming a resist film in a region of the non-volatile memory FET and a region having a gate electrode of the MOSFET formed therein, using lithography, after the step (o); and

(q) etching the first gate electrode film which is not covered with the resist film formed in the step (p), after the step (p),

wherein a value of a product of S/L and H/L is specified in a case that a line of the gate electrode of the non-volatile memory FET is set to L, a space thereof is set to S, and a height thereof is set to H so that in the step (p), a thickness of the resist film on the gate electrode of the non-volatile memory FET is set to a thickness which is not lost by the etching step of the step (q).

2. The manufacturing method for a semiconductor device according to claim 1 , wherein the first gate electrode film is a first polysilicon film, the method further comprising the following steps:

(f1) forming a CMP stopper film on the first gate electrode film after the step (e);

(f2) forming an element isolation groove in each element isolation region that isolates a plurality of the non-volatile memory FETs and a plurality of the MOSFETs from each other, after the step (f1);

(f3) burying the element isolation groove after the step (f2), and further forming an insulating film on the entire surface of the semiconductor substrate;

(f4) polishing the surface of the semiconductor substrate until the CMP stopper film is exposed, through chemical mechanical polishing (CMP), after the step (f3);

(f5) selectively removing the CMP stopper film after the step (f4); and

(g) a step of forming a second polysilicon film on the entire surface of the semiconductor substrate, after the step (f5), and

the step (q) further comprises etching the first polysilicon which is the first gate electrode film and the second polysilicon which are not covered with the resist film formed in the step (p).

3. The manufacturing method for a semiconductor device according to claim 2 , wherein a thickness of the second gate electrode film is smaller than that of a gate electrode film of the MOSFET in which the first polysilicon film and the second polysilicon film are laminated.

4. The manufacturing method for a semiconductor device according to claim 1 , wherein the first potential barrier film and the second potential barrier film are silicon oxide films, and the charge storage film is a silicon nitride film or a silicon oxynitride film.

5. A manufacturing method for a semiconductor device having a non-volatile memory FET and a MOSFET formed on a single semiconductor substrate, comprising:

forming a gate electrode film of the MOSFET in a portion of a surface of the semiconductor substrate;

patterning and forming a gate electrode of the non-volatile memory FET in another portion of the surface of the semiconductor substrate;

forming a resist film for patterning the gate electrode of the MOSFET; and

etching the gate electrode film corresponding to a portion which is not covered with the resist film,

wherein a value of a product of S/L and H/L is specified in a case that a line of the gate electrode of the non-volatile memory FET is set to L, a space thereof is set to S, and a height thereof is set to H so that thickness of the resist film on the gate electrode of the non-volatile memory FET is set to a thickness which is not lost by the etching.

6. The manufacturing method for a semiconductor device according to claim 5 , wherein the gate electrode film of the MOSFET is formed by a first polysilicon film formed before formation of an element isolation layer and a second polysilicon film formed after formation of the element isolation layer being laminated.

7. The manufacturing method for a semiconductor device according to claim 6 , wherein a thickness of a second gate electrode film is smaller than that of the gate electrode film of the MOSFET in which the first polysilicon film and the second polysilicon film are laminated.

8. The manufacturing method for a semiconductor device according to claim 5 , wherein the first potential barrier film and the second potential barrier film are silicon oxide films, and the charge storage film is a silicon nitride film or a silicon oxynitride film.