Semiconductor device and method of manufacturing the same
An embodiment of a compound semiconductor device includes: a first lower electrode; a first insulating film over the first lower electrode; a first upper electrode over the first insulating film; a second lower electrode separate from the first lower electrode; a second insulating film over the second lower electrode; a third insulating film over the second insulating film; and a second upper electrode over on the third insulating film. A thickness of the first insulating film is substantially the same as a thickness of the third insulating film, a contour of the third insulating film in planar view is outside a contour of the second insulating film in planar view, and a contour of the second upper electrode in planar view is inside the contour of the second insulating film in planar view.
1. A semiconductor device, comprising:
a first lower electrode;
a first insulating film over the first lower electrode;
a first upper electrode over the first insulating film;
a second lower electrode separate from the first lower electrode;
a second insulating film over the second lower electrode;
a third insulating film over the second insulating film; and
a second upper electrode over on the third insulating film,
wherein:
a thickness of the first insulating film is substantially the same as a thickness of the third insulating film;
a contour of the third insulating film in planar view is outside a contour of the second insulating film in planar view; and
a contour of the second upper electrode in planar view is inside the contour of the second insulating film in planar view.
2. The semiconductor device according to claim 1 , wherein each of the first insulating film, the second insulating film, and the third insulating film is a ferroelectric film.
3. The semiconductor device according to claim 1 , wherein each of the first insulating film and the third insulating film includes a plurality of films.
4. The semiconductor device according to claim 1 , wherein a distance between the contour of the third insulating film in planar view and the contour of the second insulating film in planar view is twice or more as large as the thickness of the third insulating film.
5. The semiconductor device according to claim 1 , wherein:
the first lower electrode, the first insulating film, and the first upper electrode are in a memory cell region; and
the second lower electrode, the second insulating film, the third insulating film, and the second upper electrode are in a logic circuit region.
6. The semiconductor device according to claim 1 , wherein the first insulating film and the third insulating film are formed by etching one dielectric film.
7. The semiconductor device according to claim 1 , wherein the second insulating film is thicker than the first insulating film and the third insulating film.
8. The semiconductor device according to claim 1 , wherein an area of the second upper electrode is larger than an area of the first upper electrode.
9. A method of manufacturing a semiconductor device, comprising:
forming a first conductive film;
forming a second insulating film over the first conductive film;
forming a dielectric film that covers the second insulating film over the first conductive film;
processing the dielectric film so as to form a third insulating film that covers the second insulating film over the first conductive film, and form a first insulating film separate from the third insulating film over the first conductive film;
forming a second conductive film over the first insulating film and the third insulating film;
processing the second conductive film so as to form a first upper electrode over the first insulating film, and form a second upper electrode over the third insulating film; and
processing the first conductive film so as to form a first lower electrode under the first insulating film, and form a second lower electrode under the second insulating film,
wherein:
a contour of the third insulating film in planar view is outside a contour of the second insulating film in planar view; and
a contour of the second upper electrode in planar view is inside the contour of the second insulating film in planar view.
10. The method according to claim 9 , wherein each of the first insulating film, the second insulating film, and the third insulating film is a ferroelectric film.
11. The method according to claim 9 , wherein each of the first insulating film and the third insulating film includes a plurality of films.
12. The method according to claim 9 , wherein a distance between the contour of the third insulating film in planar view and the contour of the second insulating film in planar view is set to be twice or more as large as a thickness of the third insulating film.
13. The method according to claim 9 , wherein:
the first lower electrode, the first insulating film, and the first upper electrode are formed in a memory cell region; and
the second lower electrode, the second insulating film, the third insulating film, and the second upper electrode are formed in a logic circuit region.
14. The method according to claim 9 , wherein the second insulating film is thicker than the first insulating film and the third insulating film.
15. The method according to claim 9 , wherein an area of the second upper electrode is larger than an area of the first upper electrode.